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Current Intel SOC cores use a MailBox Interface (MBI) to provide access to unit devices connected to the system fabric. This driver implements access to this interface on BayTrail platforms. This is a requirement for drivers that need access to unit registers on the platform (e.g. accessing the PUNIT for power management features such as RAPL). Serialized access is handled by all exported routines with spinlocks. The API includes 3 functions for access to unit registers: int bt_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr) int bt_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr) int bt_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) port: indicating the unit being accessed opcode: the read or write port specific opcode offset: the register offset within the port mdr: the register data to be read, written, or modified mask: bit locations in mdr to change Returns nonzero on error Note: GPU code handles access to the GFX unit. Therefore access to that unit with this driver is disallowed to avoid conflicts. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com>
91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
/*
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* intel_baytrail.h: MailBox access support for Intel BayTrail platforms
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*/
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#ifndef INTEL_BAYTRAIL_MBI_SYMS_H
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#define INTEL_BAYTRAIL_MBI_SYMS_H
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#define BT_MBI_MCR_OFFSET 0xD0
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#define BT_MBI_MDR_OFFSET 0xD4
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#define BT_MBI_MCRX_OFFSET 0xD8
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#define BT_MBI_RD_MASK 0xFEFFFFFF
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#define BT_MBI_WR_MASK 0X01000000
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#define BT_MBI_MASK_HI 0xFFFFFF00
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#define BT_MBI_MASK_LO 0x000000FF
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#define BT_MBI_ENABLE 0xF0
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/* BT-SB unit access methods */
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#define BT_MBI_UNIT_AUNIT 0x00
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#define BT_MBI_UNIT_SMC 0x01
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#define BT_MBI_UNIT_CPU 0x02
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#define BT_MBI_UNIT_BUNIT 0x03
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#define BT_MBI_UNIT_PMC 0x04
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#define BT_MBI_UNIT_GFX 0x06
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#define BT_MBI_UNIT_SMI 0x0C
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#define BT_MBI_UNIT_USB 0x43
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#define BT_MBI_UNIT_SATA 0xA3
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#define BT_MBI_UNIT_PCIE 0xA6
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/* Read/write opcodes */
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#define BT_MBI_AUNIT_READ 0x10
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#define BT_MBI_AUNIT_WRITE 0x11
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#define BT_MBI_SMC_READ 0x10
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#define BT_MBI_SMC_WRITE 0x11
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#define BT_MBI_CPU_READ 0x10
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#define BT_MBI_CPU_WRITE 0x11
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#define BT_MBI_BUNIT_READ 0x10
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#define BT_MBI_BUNIT_WRITE 0x11
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#define BT_MBI_PMC_READ 0x06
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#define BT_MBI_PMC_WRITE 0x07
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#define BT_MBI_GFX_READ 0x00
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#define BT_MBI_GFX_WRITE 0x01
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#define BT_MBI_SMIO_READ 0x06
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#define BT_MBI_SMIO_WRITE 0x07
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#define BT_MBI_USB_READ 0x06
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#define BT_MBI_USB_WRITE 0x07
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#define BT_MBI_SATA_READ 0x00
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#define BT_MBI_SATA_WRITE 0x01
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#define BT_MBI_PCIE_READ 0x00
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#define BT_MBI_PCIE_WRITE 0x01
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/**
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* bt_mbi_read() - MailBox Interface read command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data to be read
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int bt_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
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/**
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* bt_mbi_write() - MailBox unmasked write command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data to be written
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int bt_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
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/**
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* bt_mbi_modify() - MailBox masked write command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data being modified
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* @mask: mask indicating bits in mdr to be modified
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int bt_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
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#endif /* INTEL_BAYTRAIL_MBI_SYMS_H */
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