mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 20:15:30 +07:00
afb0c796d8
The clock_get() hook returns KHz, not Hz. Also fixed to use crystal freq from dev_priv. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
84 lines
1.6 KiB
C
84 lines
1.6 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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int
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nv04_timer_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 m, n, d;
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nv_wr32(dev, NV04_PTIMER_INTR_EN_0, 0x00000000);
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nv_wr32(dev, NV04_PTIMER_INTR_0, 0xFFFFFFFF);
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/* aim for 31.25MHz, which gives us nanosecond timestamps */
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d = 1000000 / 32;
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/* determine base clock for timer source */
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if (dev_priv->chipset < 0x40) {
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n = dev_priv->engine.pm.clock_get(dev, PLL_CORE);
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} else
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if (dev_priv->chipset == 0x40) {
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/*XXX: figure this out */
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n = 0;
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} else {
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n = dev_priv->crystal;
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m = 1;
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while (n < (d * 2)) {
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n += (n / m);
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m++;
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}
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nv_wr32(dev, 0x009220, m - 1);
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}
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if (!n) {
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NV_WARN(dev, "PTIMER: unknown input clock freq\n");
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if (!nv_rd32(dev, NV04_PTIMER_NUMERATOR) ||
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!nv_rd32(dev, NV04_PTIMER_DENOMINATOR)) {
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nv_wr32(dev, NV04_PTIMER_NUMERATOR, 1);
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nv_wr32(dev, NV04_PTIMER_DENOMINATOR, 1);
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}
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return 0;
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}
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/* reduce ratio to acceptable values */
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while (((n % 5) == 0) && ((d % 5) == 0)) {
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n /= 5;
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d /= 5;
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}
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while (((n % 2) == 0) && ((d % 2) == 0)) {
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n /= 2;
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d /= 2;
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}
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while (n > 0xffff || d > 0xffff) {
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n >>= 1;
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d >>= 1;
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}
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nv_wr32(dev, NV04_PTIMER_NUMERATOR, n);
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nv_wr32(dev, NV04_PTIMER_DENOMINATOR, d);
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return 0;
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}
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u64
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nv04_timer_read(struct drm_device *dev)
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{
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u32 hi, lo;
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do {
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hi = nv_rd32(dev, NV04_PTIMER_TIME_1);
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lo = nv_rd32(dev, NV04_PTIMER_TIME_0);
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} while (hi != nv_rd32(dev, NV04_PTIMER_TIME_1));
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return ((u64)hi << 32 | lo);
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}
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void
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nv04_timer_takedown(struct drm_device *dev)
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{
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}
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