mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 20:35:24 +07:00
f3f2f54e11
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_hw.h"
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#include "nouveau_pm.h"
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struct nv04_pm_state {
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struct pll_lims pll;
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struct nouveau_pll_vals calc;
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};
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int
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nv04_pm_clock_get(struct drm_device *dev, u32 id)
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{
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return nouveau_hw_get_clock(dev, id);
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}
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void *
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nv04_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
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u32 id, int khz)
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{
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struct nv04_pm_state *state;
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int ret;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (!state)
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return ERR_PTR(-ENOMEM);
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ret = get_pll_limits(dev, id, &state->pll);
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if (ret) {
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kfree(state);
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return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
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}
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ret = nouveau_calc_pll_mnp(dev, &state->pll, khz, &state->calc);
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if (!ret) {
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kfree(state);
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return ERR_PTR(-EINVAL);
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}
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return state;
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}
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void
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nv04_pm_clock_set(struct drm_device *dev, void *pre_state)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
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struct nv04_pm_state *state = pre_state;
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u32 reg = state->pll.reg;
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/* thank the insane nouveau_hw_setpll() interface for this */
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if (dev_priv->card_type >= NV_40)
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reg += 4;
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nouveau_hw_setpll(dev, reg, &state->calc);
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if (dev_priv->card_type < NV_30 && reg == NV_PRAMDAC_MPLL_COEFF) {
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if (dev_priv->card_type == NV_20)
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nv_mask(dev, 0x1002c4, 0, 1 << 20);
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/* Reset the DLLs */
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nv_mask(dev, 0x1002c0, 0, 1 << 8);
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}
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if (reg == NV_PRAMDAC_NVPLL_COEFF)
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ptimer->init(dev);
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kfree(state);
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}
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