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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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41a524abff
This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
200 lines
5.1 KiB
C
200 lines
5.1 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __KV_DPM_H__
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#define __KV_DPM_H__
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#define SMU__NUM_SCLK_DPM_STATE 8
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#define SMU__NUM_MCLK_DPM_LEVELS 4
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#define SMU__NUM_LCLK_DPM_LEVELS 8
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#define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
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#include "smu7_fusion.h"
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#include "trinity_dpm.h"
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#include "ppsmc.h"
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#define KV_NUM_NBPSTATES 4
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enum kv_pt_config_reg_type {
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KV_CONFIGREG_MMR = 0,
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KV_CONFIGREG_SMC_IND,
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KV_CONFIGREG_DIDT_IND,
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KV_CONFIGREG_CACHE,
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KV_CONFIGREG_MAX
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};
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struct kv_pt_config_reg {
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u32 offset;
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u32 mask;
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u32 shift;
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u32 value;
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enum kv_pt_config_reg_type type;
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};
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struct kv_lcac_config_values {
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u32 block_id;
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u32 signal_id;
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u32 t;
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};
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struct kv_lcac_config_reg {
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u32 cntl;
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u32 block_mask;
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u32 block_shift;
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u32 signal_mask;
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u32 signal_shift;
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u32 t_mask;
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u32 t_shift;
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u32 enable_mask;
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u32 enable_shift;
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};
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struct kv_pl {
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u32 sclk;
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u8 vddc_index;
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u8 ds_divider_index;
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u8 ss_divider_index;
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u8 allow_gnb_slow;
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u8 force_nbp_state;
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u8 display_wm;
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u8 vce_wm;
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};
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struct kv_ps {
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struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
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u32 num_levels;
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bool need_dfs_bypass;
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u8 dpm0_pg_nb_ps_lo;
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u8 dpm0_pg_nb_ps_hi;
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u8 dpmx_nb_ps_lo;
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u8 dpmx_nb_ps_hi;
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};
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struct kv_sys_info {
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u32 bootup_uma_clk;
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u32 bootup_sclk;
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u32 dentist_vco_freq;
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u32 nb_dpm_enable;
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u32 nbp_memory_clock[KV_NUM_NBPSTATES];
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u32 nbp_n_clock[KV_NUM_NBPSTATES];
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u16 bootup_nb_voltage_index;
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u8 htc_tmp_lmt;
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u8 htc_hyst_lmt;
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struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
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struct sumo_vid_mapping_table vid_mapping_table;
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u32 uma_channel_number;
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};
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struct kv_power_info {
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u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
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u32 voltage_drop_t;
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struct kv_sys_info sys_info;
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struct kv_pl boot_pl;
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bool enable_nb_ps_policy;
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bool disable_nb_ps3_in_battery;
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bool video_start;
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bool battery_state;
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u32 lowest_valid;
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u32 highest_valid;
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u16 high_voltage_t;
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bool cac_enabled;
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bool bapm_enable;
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/* smc offsets */
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u32 sram_end;
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u32 dpm_table_start;
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u32 soft_regs_start;
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/* dpm SMU tables */
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u8 graphics_dpm_level_count;
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u8 uvd_level_count;
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u8 vce_level_count;
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u8 acp_level_count;
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u8 samu_level_count;
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u16 fps_high_t;
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SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
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SMU7_Fusion_ACPILevel acpi_level;
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SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];
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SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];
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SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];
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SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];
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u8 uvd_boot_level;
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u8 vce_boot_level;
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u8 acp_boot_level;
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u8 samu_boot_level;
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u8 uvd_interval;
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u8 vce_interval;
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u8 acp_interval;
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u8 samu_interval;
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u8 graphics_boot_level;
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u8 graphics_interval;
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u8 graphics_therm_throttle_enable;
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u8 graphics_voltage_change_enable;
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u8 graphics_clk_slow_enable;
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u8 graphics_clk_slow_divider;
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u8 fps_low_t;
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u32 low_sclk_interrupt_t;
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bool uvd_power_gated;
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bool vce_power_gated;
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bool acp_power_gated;
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bool samu_power_gated;
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bool nb_dpm_enabled;
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/* flags */
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bool enable_didt;
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bool enable_dpm;
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bool enable_auto_thermal_throttling;
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bool enable_nb_dpm;
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/* caps */
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bool caps_cac;
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bool caps_power_containment;
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bool caps_sq_ramping;
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bool caps_db_ramping;
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bool caps_td_ramping;
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bool caps_tcp_ramping;
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bool caps_sclk_throttle_low_notification;
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bool caps_fps;
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bool caps_uvd_dpm;
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bool caps_uvd_pg;
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bool caps_vce_pg;
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bool caps_samu_pg;
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bool caps_acp_pg;
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bool caps_stable_p_state;
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bool caps_enable_dfs_bypass;
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bool caps_sclk_ds;
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struct radeon_ps current_rps;
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struct kv_ps current_ps;
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struct radeon_ps requested_rps;
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struct kv_ps requested_ps;
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};
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/* kv_smc.c */
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int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);
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int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
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int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
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PPSMC_Msg msg, u32 parameter);
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int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
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u32 *value, u32 limit);
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int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
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int kv_copy_bytes_to_smc(struct radeon_device *rdev,
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u32 smc_start_address,
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const u8 *src, u32 byte_count, u32 limit);
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#endif
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