mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
77a0b09dd9
Loading the firmware requires an allocation of IOVA space to make sure that the VIC's Falcon microcontroller can read the firmware if address translation via the SMMU is enabled. However, the allocation currently happens at a time where the geometry of an IOMMU domain may not have been initialized yet. This happens for example on Tegra186 and later where an ARM SMMU is used. Domains which are created by the ARM SMMU driver postpone the geometry setup until a device is attached to the domain. This is because IOMMU domains aren't attached to a specific IOMMU instance at allocation time and hence the input address space, which defines the geometry, is not known yet. Work around this by postponing the firmware load until it is needed at the time where a channel is opened to the VIC. At this time the shared IOMMU domain's geometry has been properly initialized. As a byproduct this allows the Tegra DRM to be created in the absence of VIC firmware, since the VIC initialization no longer fails if the firmware can't be found. Based on an earlier patch by Dmitry Osipenko <digetx@gmail.com>. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
484 lines
10 KiB
C
484 lines
10 KiB
C
/*
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* Copyright (c) 2015, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/host1x.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <soc/tegra/pmc.h>
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#include "drm.h"
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#include "falcon.h"
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#include "vic.h"
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struct vic_config {
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const char *firmware;
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unsigned int version;
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};
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struct vic {
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struct falcon falcon;
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bool booted;
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void __iomem *regs;
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struct tegra_drm_client client;
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struct host1x_channel *channel;
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struct iommu_domain *domain;
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struct device *dev;
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struct clk *clk;
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struct reset_control *rst;
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/* Platform configuration */
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const struct vic_config *config;
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};
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static inline struct vic *to_vic(struct tegra_drm_client *client)
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{
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return container_of(client, struct vic, client);
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}
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static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
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{
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writel(value, vic->regs + offset);
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}
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static int vic_runtime_resume(struct device *dev)
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{
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struct vic *vic = dev_get_drvdata(dev);
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int err;
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err = clk_prepare_enable(vic->clk);
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if (err < 0)
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return err;
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usleep_range(10, 20);
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err = reset_control_deassert(vic->rst);
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if (err < 0)
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goto disable;
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usleep_range(10, 20);
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return 0;
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disable:
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clk_disable_unprepare(vic->clk);
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return err;
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}
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static int vic_runtime_suspend(struct device *dev)
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{
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struct vic *vic = dev_get_drvdata(dev);
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int err;
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err = reset_control_assert(vic->rst);
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if (err < 0)
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return err;
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usleep_range(2000, 4000);
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clk_disable_unprepare(vic->clk);
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vic->booted = false;
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return 0;
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}
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static int vic_boot(struct vic *vic)
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{
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u32 fce_ucode_size, fce_bin_data_offset;
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void *hdr;
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int err = 0;
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if (vic->booted)
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return 0;
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/* setup clockgating registers */
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vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
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CG_IDLE_CG_EN |
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CG_WAKEUP_DLY_CNT(4),
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NV_PVIC_MISC_PRI_VIC_CG);
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err = falcon_boot(&vic->falcon);
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if (err < 0)
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return err;
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hdr = vic->falcon.firmware.vaddr;
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fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
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hdr = vic->falcon.firmware.vaddr +
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*(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
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fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
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falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
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falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
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fce_ucode_size);
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falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
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(vic->falcon.firmware.paddr + fce_bin_data_offset)
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>> 8);
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err = falcon_wait_idle(&vic->falcon);
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if (err < 0) {
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dev_err(vic->dev,
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"failed to set application ID and FCE base\n");
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return err;
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}
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vic->booted = true;
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return 0;
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}
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static void *vic_falcon_alloc(struct falcon *falcon, size_t size,
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dma_addr_t *iova)
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{
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struct tegra_drm *tegra = falcon->data;
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return tegra_drm_alloc(tegra, size, iova);
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}
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static void vic_falcon_free(struct falcon *falcon, size_t size,
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dma_addr_t iova, void *va)
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{
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struct tegra_drm *tegra = falcon->data;
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return tegra_drm_free(tegra, size, va, iova);
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}
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static const struct falcon_ops vic_falcon_ops = {
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.alloc = vic_falcon_alloc,
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.free = vic_falcon_free
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};
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static int vic_init(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct iommu_group *group = iommu_group_get(client->dev);
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struct drm_device *dev = dev_get_drvdata(client->parent);
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struct tegra_drm *tegra = dev->dev_private;
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struct vic *vic = to_vic(drm);
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int err;
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if (group && tegra->domain) {
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err = iommu_attach_group(tegra->domain, group);
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if (err < 0) {
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dev_err(vic->dev, "failed to attach to domain: %d\n",
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err);
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return err;
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}
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vic->domain = tegra->domain;
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}
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vic->channel = host1x_channel_request(client->dev);
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if (!vic->channel) {
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err = -ENOMEM;
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goto detach;
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}
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client->syncpts[0] = host1x_syncpt_request(client, 0);
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if (!client->syncpts[0]) {
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err = -ENOMEM;
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goto free_channel;
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}
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err = tegra_drm_register_client(tegra, drm);
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if (err < 0)
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goto free_syncpt;
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return 0;
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free_syncpt:
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host1x_syncpt_free(client->syncpts[0]);
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free_channel:
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host1x_channel_put(vic->channel);
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detach:
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if (group && tegra->domain)
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iommu_detach_group(tegra->domain, group);
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return err;
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}
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static int vic_exit(struct host1x_client *client)
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{
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struct tegra_drm_client *drm = host1x_to_drm_client(client);
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struct iommu_group *group = iommu_group_get(client->dev);
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struct drm_device *dev = dev_get_drvdata(client->parent);
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struct tegra_drm *tegra = dev->dev_private;
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struct vic *vic = to_vic(drm);
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int err;
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err = tegra_drm_unregister_client(tegra, drm);
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if (err < 0)
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return err;
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host1x_syncpt_free(client->syncpts[0]);
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host1x_channel_put(vic->channel);
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if (vic->domain) {
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iommu_detach_group(vic->domain, group);
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vic->domain = NULL;
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}
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return 0;
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}
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static const struct host1x_client_ops vic_client_ops = {
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.init = vic_init,
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.exit = vic_exit,
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};
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static int vic_load_firmware(struct vic *vic)
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{
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int err;
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if (vic->falcon.data)
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return 0;
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vic->falcon.data = vic->client.drm;
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err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
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if (err < 0)
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goto cleanup;
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err = falcon_load_firmware(&vic->falcon);
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if (err < 0)
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goto cleanup;
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return 0;
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cleanup:
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vic->falcon.data = NULL;
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return err;
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}
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static int vic_open_channel(struct tegra_drm_client *client,
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struct tegra_drm_context *context)
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{
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struct vic *vic = to_vic(client);
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int err;
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err = pm_runtime_get_sync(vic->dev);
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if (err < 0)
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return err;
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err = vic_load_firmware(vic);
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if (err < 0)
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goto rpm_put;
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err = vic_boot(vic);
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if (err < 0)
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goto rpm_put;
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context->channel = host1x_channel_get(vic->channel);
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if (!context->channel) {
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err = -ENOMEM;
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goto rpm_put;
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}
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return 0;
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rpm_put:
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pm_runtime_put(vic->dev);
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return err;
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}
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static void vic_close_channel(struct tegra_drm_context *context)
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{
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struct vic *vic = to_vic(context->client);
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host1x_channel_put(context->channel);
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pm_runtime_put(vic->dev);
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}
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static const struct tegra_drm_client_ops vic_ops = {
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.open_channel = vic_open_channel,
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.close_channel = vic_close_channel,
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.submit = tegra_drm_submit,
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};
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#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
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static const struct vic_config vic_t124_config = {
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.firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
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.version = 0x40,
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};
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#define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
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static const struct vic_config vic_t210_config = {
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.firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
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.version = 0x21,
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};
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#define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
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static const struct vic_config vic_t186_config = {
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.firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
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.version = 0x18,
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};
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#define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
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static const struct vic_config vic_t194_config = {
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.firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
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.version = 0x19,
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};
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static const struct of_device_id vic_match[] = {
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{ .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
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{ .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
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{ .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
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{ .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
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{ },
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};
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static int vic_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct host1x_syncpt **syncpts;
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struct resource *regs;
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struct vic *vic;
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int err;
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vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
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if (!vic)
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return -ENOMEM;
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vic->config = of_device_get_match_data(dev);
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syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
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if (!syncpts)
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return -ENOMEM;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!regs) {
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dev_err(&pdev->dev, "failed to get registers\n");
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return -ENXIO;
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}
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vic->regs = devm_ioremap_resource(dev, regs);
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if (IS_ERR(vic->regs))
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return PTR_ERR(vic->regs);
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vic->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(vic->clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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return PTR_ERR(vic->clk);
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}
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if (!dev->pm_domain) {
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vic->rst = devm_reset_control_get(dev, "vic");
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if (IS_ERR(vic->rst)) {
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dev_err(&pdev->dev, "failed to get reset\n");
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return PTR_ERR(vic->rst);
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}
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}
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vic->falcon.dev = dev;
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vic->falcon.regs = vic->regs;
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vic->falcon.ops = &vic_falcon_ops;
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err = falcon_init(&vic->falcon);
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if (err < 0)
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return err;
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platform_set_drvdata(pdev, vic);
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INIT_LIST_HEAD(&vic->client.base.list);
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vic->client.base.ops = &vic_client_ops;
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vic->client.base.dev = dev;
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vic->client.base.class = HOST1X_CLASS_VIC;
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vic->client.base.syncpts = syncpts;
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vic->client.base.num_syncpts = 1;
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vic->dev = dev;
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INIT_LIST_HEAD(&vic->client.list);
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vic->client.version = vic->config->version;
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vic->client.ops = &vic_ops;
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err = host1x_client_register(&vic->client.base);
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if (err < 0) {
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dev_err(dev, "failed to register host1x client: %d\n", err);
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platform_set_drvdata(pdev, NULL);
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goto exit_falcon;
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}
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pm_runtime_enable(&pdev->dev);
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if (!pm_runtime_enabled(&pdev->dev)) {
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err = vic_runtime_resume(&pdev->dev);
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if (err < 0)
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goto unregister_client;
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}
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return 0;
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unregister_client:
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host1x_client_unregister(&vic->client.base);
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exit_falcon:
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falcon_exit(&vic->falcon);
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return err;
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}
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static int vic_remove(struct platform_device *pdev)
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{
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struct vic *vic = platform_get_drvdata(pdev);
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int err;
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err = host1x_client_unregister(&vic->client.base);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
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err);
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return err;
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}
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if (pm_runtime_enabled(&pdev->dev))
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pm_runtime_disable(&pdev->dev);
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else
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vic_runtime_suspend(&pdev->dev);
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falcon_exit(&vic->falcon);
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return 0;
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}
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static const struct dev_pm_ops vic_pm_ops = {
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SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
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};
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struct platform_driver tegra_vic_driver = {
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.driver = {
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.name = "tegra-vic",
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.of_match_table = vic_match,
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.pm = &vic_pm_ops
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},
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.probe = vic_probe,
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.remove = vic_remove,
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};
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
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MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
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#endif
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
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#endif
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
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MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
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#endif
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
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MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);
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#endif
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