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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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129 lines
3.7 KiB
C
129 lines
3.7 KiB
C
/* dma.h: FRV DMA controller management
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_DMA_H
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#define _ASM_DMA_H
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//#define DMA_DEBUG 1
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#include <linux/interrupt.h>
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#undef MAX_DMA_CHANNELS /* don't use kernel/dma.c */
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/* under 2.4 this is actually needed by the new bootmem allocator */
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#define MAX_DMA_ADDRESS PAGE_OFFSET
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/*
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* FRV DMA controller management
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*/
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struct pt_regs;
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typedef irqreturn_t (*dma_irq_handler_t)(int dmachan, unsigned long cstr, void *data,
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struct pt_regs *regs);
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extern void frv_dma_init(void);
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extern int frv_dma_open(const char *devname,
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unsigned long dmamask,
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int dmacap,
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dma_irq_handler_t handler,
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unsigned long irq_flags,
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void *data);
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/* channels required */
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#define FRV_DMA_MASK_ANY ULONG_MAX /* any channel */
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/* capabilities required */
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#define FRV_DMA_CAP_DREQ 0x01 /* DMA request pin */
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#define FRV_DMA_CAP_DACK 0x02 /* DMA ACK pin */
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#define FRV_DMA_CAP_DONE 0x04 /* DMA done pin */
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extern void frv_dma_close(int dma);
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extern void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr);
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extern void frv_dma_start(int dma,
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unsigned long sba, unsigned long dba,
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unsigned long pix, unsigned long six, unsigned long bcl);
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extern void frv_dma_restart_circular(int dma, unsigned long six);
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extern void frv_dma_stop(int dma);
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extern int is_frv_dma_interrupting(int dma);
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extern void frv_dma_dump(int dma);
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extern void frv_dma_status_clear(int dma);
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#define FRV_DMA_NCHANS 8
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#define FRV_DMA_4CHANS 4
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#define FRV_DMA_8CHANS 8
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#define DMAC_CCFRx 0x00 /* channel configuration reg */
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#define DMAC_CCFRx_CM_SHIFT 16
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#define DMAC_CCFRx_CM_DA 0x00000000
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#define DMAC_CCFRx_CM_SCA 0x00010000
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#define DMAC_CCFRx_CM_DCA 0x00020000
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#define DMAC_CCFRx_CM_2D 0x00030000
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#define DMAC_CCFRx_ATS_SHIFT 8
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#define DMAC_CCFRx_RS_INTERN 0x00000000
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#define DMAC_CCFRx_RS_EXTERN 0x00000001
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#define DMAC_CCFRx_RS_SHIFT 0
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#define DMAC_CSTRx 0x08 /* channel status reg */
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#define DMAC_CSTRx_FS 0x0000003f
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#define DMAC_CSTRx_NE 0x00000100
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#define DMAC_CSTRx_FED 0x00000200
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#define DMAC_CSTRx_WER 0x00000800
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#define DMAC_CSTRx_RER 0x00001000
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#define DMAC_CSTRx_CE 0x00002000
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#define DMAC_CSTRx_INT 0x00800000
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#define DMAC_CSTRx_BUSY 0x80000000
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#define DMAC_CCTRx 0x10 /* channel control reg */
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#define DMAC_CCTRx_DSIZ_1 0x00000000
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#define DMAC_CCTRx_DSIZ_2 0x00000001
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#define DMAC_CCTRx_DSIZ_4 0x00000002
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#define DMAC_CCTRx_DSIZ_32 0x00000005
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#define DMAC_CCTRx_DAU_HOLD 0x00000000
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#define DMAC_CCTRx_DAU_INC 0x00000010
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#define DMAC_CCTRx_DAU_DEC 0x00000020
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#define DMAC_CCTRx_SSIZ_1 0x00000000
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#define DMAC_CCTRx_SSIZ_2 0x00000100
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#define DMAC_CCTRx_SSIZ_4 0x00000200
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#define DMAC_CCTRx_SSIZ_32 0x00000500
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#define DMAC_CCTRx_SAU_HOLD 0x00000000
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#define DMAC_CCTRx_SAU_INC 0x00001000
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#define DMAC_CCTRx_SAU_DEC 0x00002000
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#define DMAC_CCTRx_FC 0x08000000
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#define DMAC_CCTRx_ICE 0x10000000
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#define DMAC_CCTRx_IE 0x40000000
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#define DMAC_CCTRx_ACT 0x80000000
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#define DMAC_SBAx 0x18 /* source base address reg */
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#define DMAC_DBAx 0x20 /* data base address reg */
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#define DMAC_PIXx 0x28 /* primary index reg */
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#define DMAC_SIXx 0x30 /* secondary index reg */
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#define DMAC_BCLx 0x38 /* byte count limit reg */
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#define DMAC_APRx 0x40 /* alternate pointer reg */
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/*
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* required for PCI + MODULES
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*/
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#ifdef CONFIG_PCI
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extern int isa_dma_bridge_buggy;
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#else
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#define isa_dma_bridge_buggy (0)
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#endif
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#endif /* _ASM_DMA_H */
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