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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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37f7453a4b
Add reset property for gpio, i2c, sdmmc, nand, qspi, spi, uart, and watchdog on base socfpga and socfpga_arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
898 lines
22 KiB
Plaintext
898 lines
22 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright Altera Corporation (C) 2014. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/altr,rst-mgr-a10.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "altr,socfpga-a10-smp";
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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intc: intc@ffffd000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xffffd000 0x1000>,
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<0xffffc100 0x100>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges;
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@ffda1000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffda1000 0x1000>;
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
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<0 84 IRQ_TYPE_LEVEL_HIGH>,
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<0 85 IRQ_TYPE_LEVEL_HIGH>,
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<0 86 IRQ_TYPE_LEVEL_HIGH>,
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<0 87 IRQ_TYPE_LEVEL_HIGH>,
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<0 88 IRQ_TYPE_LEVEL_HIGH>,
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<0 89 IRQ_TYPE_LEVEL_HIGH>,
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<0 90 IRQ_TYPE_LEVEL_HIGH>,
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<0 91 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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clocks = <&l4_main_clk>;
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clock-names = "apb_pclk";
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};
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};
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base_fpga_region {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "fpga-region";
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fpga-mgr = <&fpga_mgr>;
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};
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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cb_intosc_ls_clk: cb_intosc_ls_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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f2s_free_clk: f2s_free_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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main_pll: main_pll@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-pll-clock";
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>;
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reg = <0x40>;
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main_mpu_base_clk: main_mpu_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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div-reg = <0x140 0 11>;
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};
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main_noc_base_clk: main_noc_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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div-reg = <0x144 0 11>;
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};
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main_emaca_clk: main_emaca_clk@68 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x68>;
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};
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main_emacb_clk: main_emacb_clk@6c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x6C>;
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};
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main_emac_ptp_clk: main_emac_ptp_clk@70 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x70>;
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};
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main_gpio_db_clk: main_gpio_db_clk@74 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x74>;
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};
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main_sdmmc_clk: main_sdmmc_clk@78 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk"
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;
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clocks = <&main_pll>;
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reg = <0x78>;
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};
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main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x7C>;
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};
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main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x80>;
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};
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main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x84>;
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};
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main_periph_ref_clk: main_periph_ref_clk@9c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x9C>;
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};
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};
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periph_pll: periph_pll@c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-pll-clock";
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>, <&main_periph_ref_clk>;
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reg = <0xC0>;
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peri_mpu_base_clk: peri_mpu_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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div-reg = <0x140 16 11>;
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};
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peri_noc_base_clk: peri_noc_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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div-reg = <0x144 16 11>;
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};
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peri_emaca_clk: peri_emaca_clk@e8 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xE8>;
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};
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peri_emacb_clk: peri_emacb_clk@ec {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xEC>;
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};
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peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF0>;
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};
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peri_gpio_db_clk: peri_gpio_db_clk@f4 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF4>;
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};
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peri_sdmmc_clk: peri_sdmmc_clk@f8 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF8>;
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};
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peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xFC>;
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};
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peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x100>;
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};
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peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x104>;
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};
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};
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mpu_free_clk: mpu_free_clk@60 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x60>;
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};
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noc_free_clk: noc_free_clk@64 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x64>;
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};
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s2f_user1_free_clk: s2f_user1_free_clk@104 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x104>;
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};
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sdmmc_free_clk: sdmmc_free_clk@f8 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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fixed-divider = <4>;
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reg = <0xF8>;
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};
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l4_sys_free_clk: l4_sys_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&noc_free_clk>;
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fixed-divider = <4>;
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};
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l4_main_clk: l4_main_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 0 2>;
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clk-gate = <0x48 1>;
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};
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l4_mp_clk: l4_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 8 2>;
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clk-gate = <0x48 2>;
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};
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l4_sp_clk: l4_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 16 2>;
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clk-gate = <0x48 3>;
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};
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mpu_periph_clk: mpu_periph_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&mpu_free_clk>;
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fixed-divider = <4>;
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clk-gate = <0x48 0>;
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};
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sdmmc_clk: sdmmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&sdmmc_free_clk>;
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clk-gate = <0xC8 5>;
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clk-phase = <0 135>;
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};
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qspi_clk: qspi_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_main_clk>;
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clk-gate = <0xC8 11>;
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};
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nand_x_clk: nand_x_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_mp_clk>;
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clk-gate = <0xC8 10>;
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};
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nand_ecc_clk: nand_ecc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&nand_x_clk>;
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clk-gate = <0xC8 10>;
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};
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nand_clk: nand_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&nand_x_clk>;
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fixed-divider = <4>;
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clk-gate = <0xC8 10>;
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};
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spi_m_clk: spi_m_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_main_clk>;
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clk-gate = <0xC8 9>;
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};
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usb_clk: usb_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_mp_clk>;
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clk-gate = <0xC8 8>;
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};
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s2f_usr1_clk: s2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&peri_s2f_usr1_clk>;
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clk-gate = <0xC8 6>;
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};
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};
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};
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socfpga_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <0xf>;
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snps,rd_osr_lmt = <0xf>;
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snps,blen = <0 0 0 0 16 0 0>;
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};
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gmac0: ethernet@ff800000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x44 0>;
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reg = <0xff800000 0x2000>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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/* Filled in by bootloader */
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mac-address = [00 00 00 00 00 00];
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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tx-fifo-depth = <4096>;
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rx-fifo-depth = <16384>;
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clocks = <&l4_mp_clk>;
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clock-names = "stmmaceth";
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resets = <&rst EMAC0_RESET>;
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reset-names = "stmmaceth";
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snps,axi-config = <&socfpga_axi_setup>;
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status = "disabled";
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};
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gmac1: ethernet@ff802000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x48 0>;
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reg = <0xff802000 0x2000>;
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interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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/* Filled in by bootloader */
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mac-address = [00 00 00 00 00 00];
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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tx-fifo-depth = <4096>;
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rx-fifo-depth = <16384>;
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clocks = <&l4_mp_clk>;
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clock-names = "stmmaceth";
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resets = <&rst EMAC1_RESET>;
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reset-names = "stmmaceth";
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snps,axi-config = <&socfpga_axi_setup>;
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status = "disabled";
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};
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gmac2: ethernet@ff804000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
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reg = <0xff804000 0x2000>;
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interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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/* Filled in by bootloader */
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mac-address = [00 00 00 00 00 00];
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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tx-fifo-depth = <4096>;
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rx-fifo-depth = <16384>;
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clocks = <&l4_mp_clk>;
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resets = <&rst EMAC2_RESET>;
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clock-names = "stmmaceth";
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snps,axi-config = <&socfpga_axi_setup>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio0: gpio@ffc02900 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xffc02900 0x100>;
|
|
resets = <&rst GPIO0_RESET>;
|
|
status = "disabled";
|
|
|
|
porta: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <29>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
gpio1: gpio@ffc02a00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xffc02a00 0x100>;
|
|
resets = <&rst GPIO1_RESET>;
|
|
status = "disabled";
|
|
|
|
portb: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <29>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
gpio2: gpio@ffc02b00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0xffc02b00 0x100>;
|
|
resets = <&rst GPIO2_RESET>;
|
|
status = "disabled";
|
|
|
|
portc: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-port";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
snps,nr-gpios = <27>;
|
|
reg = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
fpga_mgr: fpga-mgr@ffd03000 {
|
|
compatible = "altr,socfpga-a10-fpga-mgr";
|
|
reg = <0xffd03000 0x100
|
|
0xffcfe400 0x20>;
|
|
clocks = <&l4_mp_clk>;
|
|
resets = <&rst FPGAMGR_RESET>;
|
|
reset-names = "fpgamgr";
|
|
};
|
|
|
|
i2c0: i2c@ffc02200 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xffc02200 0x100>;
|
|
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&l4_sp_clk>;
|
|
resets = <&rst I2C0_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@ffc02300 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xffc02300 0x100>;
|
|
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&l4_sp_clk>;
|
|
resets = <&rst I2C1_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@ffc02400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xffc02400 0x100>;
|
|
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&l4_sp_clk>;
|
|
resets = <&rst I2C2_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@ffc02500 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xffc02500 0x100>;
|
|
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&l4_sp_clk>;
|
|
resets = <&rst I2C3_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@ffc02600 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0xffc02600 0x100>;
|
|
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&l4_sp_clk>;
|
|
resets = <&rst I2C4_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@ffda4000 {
|
|
compatible = "snps,dw-apb-ssi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xffda4000 0x100>;
|
|
interrupts = <0 101 4>;
|
|
num-cs = <4>;
|
|
/*32bit_access;*/
|
|
clocks = <&spi_m_clk>;
|
|
resets = <&rst SPIM0_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@ffda5000 {
|
|
compatible = "snps,dw-apb-ssi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xffda5000 0x100>;
|
|
interrupts = <0 102 4>;
|
|
num-cs = <4>;
|
|
/*32bit_access;*/
|
|
tx-dma-channel = <&pdma 16>;
|
|
rx-dma-channel = <&pdma 17>;
|
|
clocks = <&spi_m_clk>;
|
|
resets = <&rst SPIM1_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdr: sdr@ffcfb100 {
|
|
compatible = "altr,sdr-ctl", "syscon";
|
|
reg = <0xffcfb100 0x80>;
|
|
};
|
|
|
|
L2: l2-cache@fffff000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0xfffff000 0x1000>;
|
|
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
prefetch-data = <1>;
|
|
prefetch-instr = <1>;
|
|
arm,shared-override;
|
|
};
|
|
|
|
mmc: dwmmc0@ff808000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "altr,socfpga-dw-mshc";
|
|
reg = <0xff808000 0x1000>;
|
|
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
fifo-depth = <0x400>;
|
|
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
|
|
clock-names = "biu", "ciu";
|
|
resets = <&rst SDMMC_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nand: nand@ffb90000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "altr,socfpga-denali-nand";
|
|
reg = <0xffb90000 0x72000>,
|
|
<0xffb80000 0x10000>;
|
|
reg-names = "nand_data", "denali_reg";
|
|
interrupts = <0 99 4>;
|
|
clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
|
|
clock-names = "nand", "nand_x", "ecc";
|
|
resets = <&rst NAND_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ocram: sram@ffe00000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xffe00000 0x40000>;
|
|
};
|
|
|
|
eccmgr: eccmgr {
|
|
compatible = "altr,socfpga-a10-ecc-manager";
|
|
altr,sysmgr-syscon = <&sysmgr>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ranges;
|
|
|
|
sdramedac {
|
|
compatible = "altr,sdram-edac-a10";
|
|
altr,sdr-syscon = <&sdr>;
|
|
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
|
|
<49 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
l2-ecc@ffd06010 {
|
|
compatible = "altr,socfpga-a10-l2-ecc";
|
|
reg = <0xffd06010 0x4>;
|
|
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<32 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
ocram-ecc@ff8c3000 {
|
|
compatible = "altr,socfpga-a10-ocram-ecc";
|
|
reg = <0xff8c3000 0x400>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<33 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
emac0-rx-ecc@ff8c0800 {
|
|
compatible = "altr,socfpga-eth-mac-ecc";
|
|
reg = <0xff8c0800 0x400>;
|
|
altr,ecc-parent = <&gmac0>;
|
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<36 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
emac0-tx-ecc@ff8c0c00 {
|
|
compatible = "altr,socfpga-eth-mac-ecc";
|
|
reg = <0xff8c0c00 0x400>;
|
|
altr,ecc-parent = <&gmac0>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
|
|
<37 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
dma-ecc@ff8c8000 {
|
|
compatible = "altr,socfpga-dma-ecc";
|
|
reg = <0xff8c8000 0x400>;
|
|
altr,ecc-parent = <&pdma>;
|
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
|
|
<42 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
usb0-ecc@ff8c8800 {
|
|
compatible = "altr,socfpga-usb-ecc";
|
|
reg = <0xff8c8800 0x400>;
|
|
altr,ecc-parent = <&usb0>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<34 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
qspi: spi@ff809000 {
|
|
compatible = "cdns,qspi-nor";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xff809000 0x100>,
|
|
<0xffa00000 0x100000>;
|
|
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
cdns,fifo-depth = <128>;
|
|
cdns,fifo-width = <4>;
|
|
cdns,trigger-address = <0x00000000>;
|
|
clocks = <&qspi_clk>;
|
|
resets = <&rst QSPI_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rst: rstmgr@ffd05000 {
|
|
#reset-cells = <1>;
|
|
compatible = "altr,rst-mgr";
|
|
reg = <0xffd05000 0x100>;
|
|
altr,modrst-offset = <0x20>;
|
|
};
|
|
|
|
scu: snoop-control-unit@ffffc000 {
|
|
compatible = "arm,cortex-a9-scu";
|
|
reg = <0xffffc000 0x100>;
|
|
};
|
|
|
|
sysmgr: sysmgr@ffd06000 {
|
|
compatible = "altr,sys-mgr", "syscon";
|
|
reg = <0xffd06000 0x300>;
|
|
cpu1-start-addr = <0xffd06230>;
|
|
};
|
|
|
|
/* Local timer */
|
|
timer@ffffc600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0xffffc600 0x100>;
|
|
interrupts = <1 13 0xf01>;
|
|
clocks = <&mpu_periph_clk>;
|
|
};
|
|
|
|
timer0: timer0@ffc02700 {
|
|
compatible = "snps,dw-apb-timer";
|
|
interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xffc02700 0x100>;
|
|
clocks = <&l4_sp_clk>;
|
|
clock-names = "timer";
|
|
resets = <&rst SPTIMER0_RESET>;
|
|
reset-names = "timer";
|
|
};
|
|
|
|
timer1: timer1@ffc02800 {
|
|
compatible = "snps,dw-apb-timer";
|
|
interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xffc02800 0x100>;
|
|
clocks = <&l4_sp_clk>;
|
|
clock-names = "timer";
|
|
resets = <&rst SPTIMER1_RESET>;
|
|
reset-names = "timer";
|
|
};
|
|
|
|
timer2: timer2@ffd00000 {
|
|
compatible = "snps,dw-apb-timer";
|
|
interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xffd00000 0x100>;
|
|
clocks = <&l4_sys_free_clk>;
|
|
clock-names = "timer";
|
|
resets = <&rst L4SYSTIMER0_RESET>;
|
|
reset-names = "timer";
|
|
};
|
|
|
|
timer3: timer3@ffd00100 {
|
|
compatible = "snps,dw-apb-timer";
|
|
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0xffd01000 0x100>;
|
|
clocks = <&l4_sys_free_clk>;
|
|
clock-names = "timer";
|
|
resets = <&rst L4SYSTIMER1_RESET>;
|
|
reset-names = "timer";
|
|
};
|
|
|
|
uart0: serial0@ffc02000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xffc02000 0x100>;
|
|
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&l4_sp_clk>;
|
|
resets = <&rst UART0_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial1@ffc02100 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xffc02100 0x100>;
|
|
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&l4_sp_clk>;
|
|
resets = <&rst UART1_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy0: usbphy {
|
|
#phy-cells = <0>;
|
|
compatible = "usb-nop-xceiv";
|
|
status = "okay";
|
|
};
|
|
|
|
usb0: usb@ffb00000 {
|
|
compatible = "snps,dwc2";
|
|
reg = <0xffb00000 0xffff>;
|
|
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&usb_clk>;
|
|
clock-names = "otg";
|
|
resets = <&rst USB0_RESET>;
|
|
reset-names = "dwc2";
|
|
phys = <&usbphy0>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: usb@ffb40000 {
|
|
compatible = "snps,dwc2";
|
|
reg = <0xffb40000 0xffff>;
|
|
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&usb_clk>;
|
|
clock-names = "otg";
|
|
resets = <&rst USB1_RESET>;
|
|
reset-names = "dwc2";
|
|
phys = <&usbphy0>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog0: watchdog@ffd00200 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xffd00200 0x100>;
|
|
interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&l4_sys_free_clk>;
|
|
resets = <&rst L4WD0_RESET>;
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog1: watchdog@ffd00300 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xffd00300 0x100>;
|
|
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&l4_sys_free_clk>;
|
|
resets = <&rst L4WD1_RESET>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|