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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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785e5c616c
This adds support for the MediaTek hardware accelerator on mt7623/mt2701/mt8521p SoC. This driver currently implement: - SHA1 and SHA2 family(HMAC) hash algorithms. - AES block cipher in CBC/ECB mode with 128/196/256 bits keys. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
195 lines
6.5 KiB
C
195 lines
6.5 KiB
C
/*
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* Support for MediaTek cryptographic accelerator.
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*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*
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*/
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#ifndef __MTK_REGS_H__
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#define __MTK_REGS_H__
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/* HIA, Command Descriptor Ring Manager */
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#define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
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#define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
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#define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
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#define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
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#define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
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#define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12))
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#define CDR_RING_SIZE(x) (0x18 + ((x) << 12))
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#define CDR_DESC_SIZE(x) (0x1C + ((x) << 12))
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#define CDR_CFG(x) (0x20 + ((x) << 12))
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#define CDR_DMA_CFG(x) (0x24 + ((x) << 12))
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#define CDR_THRESH(x) (0x28 + ((x) << 12))
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#define CDR_PREP_COUNT(x) (0x2C + ((x) << 12))
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#define CDR_PROC_COUNT(x) (0x30 + ((x) << 12))
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#define CDR_PREP_PNTR(x) (0x34 + ((x) << 12))
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#define CDR_PROC_PNTR(x) (0x38 + ((x) << 12))
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#define CDR_STAT(x) (0x3C + ((x) << 12))
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/* HIA, Result Descriptor Ring Manager */
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#define RDR_BASE_ADDR_LO(x) (0x800 + ((x) << 12))
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#define RDR_BASE_ADDR_HI(x) (0x804 + ((x) << 12))
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#define RDR_DATA_BASE_ADDR_LO(x) (0x808 + ((x) << 12))
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#define RDR_DATA_BASE_ADDR_HI(x) (0x80C + ((x) << 12))
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#define RDR_ACD_BASE_ADDR_LO(x) (0x810 + ((x) << 12))
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#define RDR_ACD_BASE_ADDR_HI(x) (0x814 + ((x) << 12))
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#define RDR_RING_SIZE(x) (0x818 + ((x) << 12))
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#define RDR_DESC_SIZE(x) (0x81C + ((x) << 12))
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#define RDR_CFG(x) (0x820 + ((x) << 12))
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#define RDR_DMA_CFG(x) (0x824 + ((x) << 12))
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#define RDR_THRESH(x) (0x828 + ((x) << 12))
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#define RDR_PREP_COUNT(x) (0x82C + ((x) << 12))
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#define RDR_PROC_COUNT(x) (0x830 + ((x) << 12))
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#define RDR_PREP_PNTR(x) (0x834 + ((x) << 12))
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#define RDR_PROC_PNTR(x) (0x838 + ((x) << 12))
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#define RDR_STAT(x) (0x83C + ((x) << 12))
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/* HIA, Ring AIC */
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#define AIC_POL_CTRL(x) (0xE000 - ((x) << 12))
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#define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12))
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#define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12))
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#define AIC_RAW_STAL(x) (0xE00C - ((x) << 12))
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#define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12))
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#define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12))
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#define AIC_ACK(x) (0xE010 - ((x) << 12))
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#define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12))
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#define AIC_OPTIONS(x) (0xE018 - ((x) << 12))
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#define AIC_VERSION(x) (0xE01C - ((x) << 12))
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/* HIA, Global AIC */
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#define AIC_G_POL_CTRL 0xF800
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#define AIC_G_TYPE_CTRL 0xF804
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#define AIC_G_ENABLE_CTRL 0xF808
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#define AIC_G_RAW_STAT 0xF80C
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#define AIC_G_ENABLE_SET 0xF80C
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#define AIC_G_ENABLED_STAT 0xF810
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#define AIC_G_ACK 0xF810
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#define AIC_G_ENABLE_CLR 0xF814
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#define AIC_G_OPTIONS 0xF818
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#define AIC_G_VERSION 0xF81C
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/* HIA, Data Fetch Engine */
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#define DFE_CFG 0xF000
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#define DFE_PRIO_0 0xF010
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#define DFE_PRIO_1 0xF014
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#define DFE_PRIO_2 0xF018
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#define DFE_PRIO_3 0xF01C
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/* HIA, Data Fetch Engine access monitoring for CDR */
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#define DFE_RING_REGION_LO(x) (0xF080 + ((x) << 3))
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#define DFE_RING_REGION_HI(x) (0xF084 + ((x) << 3))
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/* HIA, Data Fetch Engine thread control and status for thread */
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#define DFE_THR_CTRL 0xF200
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#define DFE_THR_STAT 0xF204
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#define DFE_THR_DESC_CTRL 0xF208
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#define DFE_THR_DESC_DPTR_LO 0xF210
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#define DFE_THR_DESC_DPTR_HI 0xF214
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#define DFE_THR_DESC_ACDPTR_LO 0xF218
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#define DFE_THR_DESC_ACDPTR_HI 0xF21C
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/* HIA, Data Store Engine */
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#define DSE_CFG 0xF400
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#define DSE_PRIO_0 0xF410
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#define DSE_PRIO_1 0xF414
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#define DSE_PRIO_2 0xF418
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#define DSE_PRIO_3 0xF41C
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/* HIA, Data Store Engine access monitoring for RDR */
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#define DSE_RING_REGION_LO(x) (0xF480 + ((x) << 3))
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#define DSE_RING_REGION_HI(x) (0xF484 + ((x) << 3))
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/* HIA, Data Store Engine thread control and status for thread */
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#define DSE_THR_CTRL 0xF600
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#define DSE_THR_STAT 0xF604
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#define DSE_THR_DESC_CTRL 0xF608
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#define DSE_THR_DESC_DPTR_LO 0xF610
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#define DSE_THR_DESC_DPTR_HI 0xF614
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#define DSE_THR_DESC_S_DPTR_LO 0xF618
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#define DSE_THR_DESC_S_DPTR_HI 0xF61C
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#define DSE_THR_ERROR_STAT 0xF620
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/* HIA Global */
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#define HIA_MST_CTRL 0xFFF4
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#define HIA_OPTIONS 0xFFF8
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#define HIA_VERSION 0xFFFC
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/* Processing Engine Input Side, Processing Engine */
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#define PE_IN_DBUF_THRESH 0x10000
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#define PE_IN_TBUF_THRESH 0x10100
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/* Packet Engine Configuration / Status Registers */
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#define PE_TOKEN_CTRL_STAT 0x11000
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#define PE_FUNCTION_EN 0x11004
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#define PE_CONTEXT_CTRL 0x11008
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#define PE_INTERRUPT_CTRL_STAT 0x11010
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#define PE_CONTEXT_STAT 0x1100C
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#define PE_OUT_TRANS_CTRL_STAT 0x11018
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#define PE_OUT_BUF_CTRL 0x1101C
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/* Packet Engine PRNG Registers */
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#define PE_PRNG_STAT 0x11040
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#define PE_PRNG_CTRL 0x11044
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#define PE_PRNG_SEED_L 0x11048
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#define PE_PRNG_SEED_H 0x1104C
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#define PE_PRNG_KEY_0_L 0x11050
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#define PE_PRNG_KEY_0_H 0x11054
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#define PE_PRNG_KEY_1_L 0x11058
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#define PE_PRNG_KEY_1_H 0x1105C
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#define PE_PRNG_RES_0 0x11060
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#define PE_PRNG_RES_1 0x11064
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#define PE_PRNG_RES_2 0x11068
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#define PE_PRNG_RES_3 0x1106C
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#define PE_PRNG_LFSR_L 0x11070
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#define PE_PRNG_LFSR_H 0x11074
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/* Packet Engine AIC */
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#define PE_EIP96_AIC_POL_CTRL 0x113C0
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#define PE_EIP96_AIC_TYPE_CTRL 0x113C4
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#define PE_EIP96_AIC_ENABLE_CTRL 0x113C8
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#define PE_EIP96_AIC_RAW_STAT 0x113CC
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#define PE_EIP96_AIC_ENABLE_SET 0x113CC
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#define PE_EIP96_AIC_ENABLED_STAT 0x113D0
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#define PE_EIP96_AIC_ACK 0x113D0
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#define PE_EIP96_AIC_ENABLE_CLR 0x113D4
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#define PE_EIP96_AIC_OPTIONS 0x113D8
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#define PE_EIP96_AIC_VERSION 0x113DC
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/* Packet Engine Options & Version Registers */
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#define PE_EIP96_OPTIONS 0x113F8
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#define PE_EIP96_VERSION 0x113FC
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/* Processing Engine Output Side */
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#define PE_OUT_DBUF_THRESH 0x11C00
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#define PE_OUT_TBUF_THRESH 0x11D00
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/* Processing Engine Local AIC */
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#define PE_AIC_POL_CTRL 0x11F00
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#define PE_AIC_TYPE_CTRL 0x11F04
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#define PE_AIC_ENABLE_CTRL 0x11F08
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#define PE_AIC_RAW_STAT 0x11F0C
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#define PE_AIC_ENABLE_SET 0x11F0C
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#define PE_AIC_ENABLED_STAT 0x11F10
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#define PE_AIC_ENABLE_CLR 0x11F14
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#define PE_AIC_OPTIONS 0x11F18
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#define PE_AIC_VERSION 0x11F1C
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/* Processing Engine General Configuration and Version */
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#define PE_IN_FLIGHT 0x11FF0
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#define PE_OPTIONS 0x11FF8
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#define PE_VERSION 0x11FFC
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/* EIP-97 - Global */
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#define EIP97_CLOCK_STATE 0x1FFE4
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#define EIP97_FORCE_CLOCK_ON 0x1FFE8
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#define EIP97_FORCE_CLOCK_OFF 0x1FFEC
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#define EIP97_MST_CTRL 0x1FFF4
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#define EIP97_OPTIONS 0x1FFF8
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#define EIP97_VERSION 0x1FFFC
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#endif /* __MTK_REGS_H__ */
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