AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-21 12:26:47 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity
775d2418f3
linux_dsm_epyc7002/arch/arm/boot/dts/armada-xp-mv78260.dtsi
Olof Johansson 6cbe0e1fea mvebu dt changes for v3.12 
- kirkwood
     - add ZyXEL NSA310 board, fan for ReadyNAS Duo v2
 
  - mvebu
     - add ReadyNAS 102 board
 
  - misc dts updates and changes.
 
 v2:
  - dropped mv64xxx-i2c change
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.20 (GNU/Linux)
 
 iQEcBAABAgAGBQJSDiMPAAoJEAi3KVZQDZAenzYH+QEhluZYpiGjeo60RchyzYzx
 sKcNiGiUgZs1KAcONFIaKpTYoKjm8SSKiboegJhIYSN3NxYIm0Rlogjdl012p1zw
 vAR1dphum+xeTrvZLtiOZjfXA8XtSq+EBwkP4+CunAFXMPcyaqUW7MsxleIqCgGG
 GhSyT0APhsMBhIuvzsrBILZWPpriReiunM4rclU629xyzzrwHMxh7hrTpsw4qIgD
 ynZFRN5qJMLcFrRQ0nJVmhSyFMllYeAou5y8rXyUrde/sTI6ycMSG112ti2X3qQe
 pWEkiTnMSUajV4Adv3ljATMokDv2eMuNAEaq57k7w4njcYzNskfuhzTURy38xM0=
 =T/Dr
 -----END PGP SIGNATURE-----

Merge tag 'dt-3.12' of git://git.infradead.org/linux-mvebu into next/soc

From Jason Cooper:
mvebu dt changes for v3.12
 - kirkwood
    - add ZyXEL NSA310 board, fan for ReadyNAS Duo v2
 - mvebu
    - add ReadyNAS 102 board
 - misc dts updates and changes.

v2:
 - dropped mv64xxx-i2c change

* tag 'dt-3.12' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Fix the Armada 370/XP timer compatible strings
  ARM: mvebu: use dts pre-processor for readynas 102
  ARM: kirkwood: use dts pre-processor for nsa310 boards
  ARM: mvebu: use correct #interrupt-cells instead of #interrupts-cells
  ARM: Kirkwood: Add support for another ZyXEL NSA310 variant
  ARM: mvebu: Add Netgear ReadyNAS 102 board
  arm: kirkwood: readynas duo v2: Add GMT G762 Fan Controller

Signed-off-by: Olof Johansson <olof@lixom.net>

Conflicts:
	arch/arm/boot/dts/kirkwood-nsa310.dts
2013-08-29 10:01:40 -07:00

242 lines
6.9 KiB
Plaintext
Raw Blame History

/*
* Device Tree Include file for Marvell Armada XP family SoC
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Contains definitions specific to the Armada XP MV78260 SoC that are not
* common to all Armada XP SoCs.
*/
#include "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78260 SoC";
compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
};
soc {
/*
* MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
};
};
internal-regs {
pinctrl {
compatible = "marvell,mv78260-pinctrl";
reg = <0x18000 0x38>;
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <91>;
};
ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x4000>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
};
};
};
};
Reference in New Issue View Git Blame Copy Permalink