mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 16:39:53 +07:00
7f698bf60e
The second channel of the display unit uses a different module clock
than the first channel.
Fixes: 876e7fb9f4 ("ARM: shmobile: r8a7794: alt: Enable VGA port")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
418 lines
7.3 KiB
Plaintext
418 lines
7.3 KiB
Plaintext
/*
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* Device Tree Source for the Alt board
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a7794.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Alt";
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compatible = "renesas,alt", "renesas,r8a7794";
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aliases {
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serial0 = &scif2;
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i2c10 = &gpioi2c4;
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i2c12 = &i2cexio4;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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d3_3v: regulator-d3-3v {
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compatible = "regulator-fixed";
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regulator-name = "D3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vcc_sdhi0: regulator-vcc-sdhi0 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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vcc_sdhi1: regulator-vcc-sdhi1 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI1 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi1: regulator-vccq-sdhi1 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI1 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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lbsc {
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#address-cells = <1>;
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#size-cells = <1>;
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};
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vga-encoder {
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compatible = "adi,adv7123";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7123_in: endpoint {
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remote-endpoint = <&du_out_rgb1>;
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};
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};
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port@1 {
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reg = <1>;
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adv7123_out: endpoint {
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remote-endpoint = <&vga_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_in: endpoint {
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remote-endpoint = <&adv7123_out>;
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};
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};
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};
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x2_clk: x2-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <74250000>;
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};
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x13_clk: x13-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <148500000>;
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};
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gpioi2c4: i2c-10 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "i2c-gpio";
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status = "disabled";
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gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
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&gpio4 8 GPIO_ACTIVE_HIGH /* scl */
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>;
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i2c-gpio,delay-us = <5>;
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};
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/*
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* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
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* A fallback to GPIO is provided.
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*/
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i2cexio4: i2c-14 {
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compatible = "i2c-demux-pinctrl";
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i2c-parent = <&i2c4>, <&gpioi2c4>;
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i2c-bus-name = "i2c-exio4";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&mstp7_clks R8A7794_CLK_DU0>,
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<&mstp7_clks R8A7794_CLK_DU1>,
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<&x13_clk>, <&x2_clk>;
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clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
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ports {
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port@1 {
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endpoint {
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remote-endpoint = <&adv7123_in>;
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};
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};
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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du_pins: du {
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groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
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function = "du1";
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};
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scif2_pins: scif2 {
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groups = "scif2_data";
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function = "scif2";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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ether_pins: ether {
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groups = "eth_link", "eth_mdio", "eth_rmii";
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function = "eth";
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};
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phy1_pins: phy1 {
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groups = "intc_irq8";
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function = "intc";
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};
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i2c1_pins: i2c1 {
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groups = "i2c1";
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function = "i2c1";
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};
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i2c4_pins: i2c4 {
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groups = "i2c4";
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function = "i2c4";
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};
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vin0_pins: vin0 {
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groups = "vin0_data8", "vin0_clk";
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function = "vin0";
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};
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mmcif0_pins: mmcif0 {
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groups = "mmc_data8", "mmc_ctrl";
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function = "mmc";
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};
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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sdhi0_pins_uhs: sd0_uhs {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <1800>;
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};
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sdhi1_pins: sd1 {
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groups = "sdhi1_data4", "sdhi1_ctrl";
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function = "sdhi1";
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power-source = <3300>;
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};
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sdhi1_pins_uhs: sd1_uhs {
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groups = "sdhi1_data4", "sdhi1_ctrl";
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function = "sdhi1";
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power-source = <1800>;
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};
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};
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&cmt0 {
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status = "okay";
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};
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&pfc {
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qspi_pins: qspi {
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groups = "qspi_ctrl", "qspi_data4";
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function = "qspi";
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};
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};
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ðer {
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pinctrl-0 = <ðer_pins &phy1_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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renesas,ether-link-active-low;
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&irqc0>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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micrel,led-mode = <1>;
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};
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};
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&mmcif0 {
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pinctrl-0 = <&mmcif0_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&d3_3v>;
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vqmmc-supply = <&d3_3v>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-1 = <&sdhi0_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi0>;
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vqmmc-supply = <&vccq_sdhi0>;
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cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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&sdhi1 {
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pinctrl-0 = <&sdhi1_pins>;
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pinctrl-1 = <&sdhi1_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi1>;
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vqmmc-supply = <&vccq_sdhi1>;
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cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
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sd-uhs-sdr50;
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status = "okay";
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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composite-in@20 {
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compatible = "adi,adv7180";
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reg = <0x20>;
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remote = <&vin0>;
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port {
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adv7180: endpoint {
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bus-width = <8>;
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remote-endpoint = <&vin0ep>;
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};
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};
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};
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};
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&i2c4 {
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pinctrl-0 = <&i2c4_pins>;
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pinctrl-names = "i2c-exio4";
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};
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&vin0 {
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status = "okay";
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pinctrl-0 = <&vin0_pins>;
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pinctrl-names = "default";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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vin0ep: endpoint {
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remote-endpoint = <&adv7180>;
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bus-width = <8>;
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};
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};
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <14745600>;
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};
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&qspi {
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pinctrl-0 = <&qspi_pins>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "spansion,s25fl512s", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <30000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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spi-cpol;
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spi-cpha;
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m25p,fast-read;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "loader";
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reg = <0x00000000 0x00040000>;
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read-only;
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};
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partition@40000 {
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label = "system";
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reg = <0x00040000 0x00040000>;
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read-only;
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};
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partition@80000 {
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label = "user";
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reg = <0x00080000 0x03f80000>;
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};
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};
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};
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};
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