mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 13:22:51 +07:00
5601ca471f
Commit 599c376c49 ("ARM: dts: Fix gpio interrupts for dm816x")
corrected some problems with the MMC. However, it gets the write
protect pin backwards. It needs to be ACTIVE_HIGH not ACTIVE_LOW.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mihail Grigorov <michael.grigorov@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
218 lines
5.8 KiB
Plaintext
218 lines
5.8 KiB
Plaintext
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dm816x.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "DM8168 EVM";
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compatible = "ti,dm8168-evm", "ti,dm8168";
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x40000000 /* 1 GB */
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0xc0000000 0x40000000>; /* 1 GB */
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};
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/* FDC6331L controlled by SD_POW pin */
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vmmcsd_fixed: fixedregulator0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmcsd_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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sata_refclk: fixedclock0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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};
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&dm816x_pinmux {
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mcspi1_pins: pinmux_mcspi1_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */
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DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */
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DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */
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DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */
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>;
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};
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mmc_pins: pinmux_mmc_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
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DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
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DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
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DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
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DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
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DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
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DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
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DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
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DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
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>;
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};
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usb0_pins: pinmux_usb0_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */
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>;
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};
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usb1_pins: pinmux_usb1_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
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>;
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};
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nandflash_pins: nandflash_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/
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DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */
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DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */
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DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */
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DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */
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DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */
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DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */
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DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */
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DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */
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DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */
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DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */
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DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */
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DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */
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DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */
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DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */
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DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */
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DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */
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DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */
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DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */
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DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */
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DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */
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DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */
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DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */
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>;
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};
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};
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&i2c1 {
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extgpio0: pcf8575@20 {
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compatible = "nxp,pcf8575";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&i2c2 {
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extgpio1: pcf8575@20 {
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compatible = "nxp,pcf8575";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&gpmc {
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ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
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pinctrl-names = "default";
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pinctrl-0 = <&nandflash_pins>;
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nand@0,0 {
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compatible = "ti,omap2-nand";
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linux,mtd-name= "micron,mt29f2g16aadwp";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
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#address-cells = <1>;
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#size-cells = <1>;
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-on-ns = <0>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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partition@0 {
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label = "X-Loader";
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reg = <0 0x80000>;
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};
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partition@0x80000 {
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label = "U-Boot";
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reg = <0x80000 0x1c0000>;
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};
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partition@0x1c0000 {
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label = "Environment";
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reg = <0x240000 0x40000>;
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};
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partition@0x280000 {
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label = "Kernel";
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reg = <0x280000 0x500000>;
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};
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partition@0x780000 {
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label = "Filesystem";
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reg = <0x780000 0xf880000>;
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};
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};
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};
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&mcspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcspi1_pins>;
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m25p80@0 {
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compatible = "w25x32";
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spi-max-frequency = <48000000>;
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc_pins>;
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vmmc-supply = <&vmmcsd_fixed>;
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bus-width = <4>;
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cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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};
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/* At least dm8168-evm rev c won't support multipoint, later may */
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&usb0 {
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pinctrl-names = "default";
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pinctrl-0 = <&usb0_pins>;
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mentor,multipoint = <0>;
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};
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&usb1 {
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pinctrl-names = "default";
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pinctrl-0 = <&usb1_pins>;
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mentor,multipoint = <0>;
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};
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&sata {
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clocks = <&sysclk5_ck>, <&sata_refclk>;
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};
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