mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 06:36:46 +07:00
fa5691131a
Many drivers are defining a DRV_VERSION. This is often only used for MODULE_VERSION and sometimes to print an info message at probe time. This is kind of pointless as they are all versionned with the kernel anyway. Also the core will print a message when a new rtc is found. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
474 lines
12 KiB
C
474 lines
12 KiB
C
/*
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* An SPI driver for the Philips PCF2123 RTC
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* Copyright 2009 Cyber Switching, Inc.
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*
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* Author: Chris Verges <chrisv@cyberswitching.com>
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* Maintainers: http://www.cyberswitching.com
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*
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* based on the RS5C348 driver in this same directory.
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*
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* Thanks to Christian Pellegrin <chripell@fsfe.org> for
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* the sysfs contributions to this driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Please note that the CS is active high, so platform data
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* should look something like:
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*
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* static struct spi_board_info ek_spi_devices[] = {
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* ...
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* {
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* .modalias = "rtc-pcf2123",
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* .chip_select = 1,
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* .controller_data = (void *)AT91_PIN_PA10,
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* .max_speed_hz = 1000 * 1000,
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* .mode = SPI_CS_HIGH,
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* .bus_num = 0,
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* },
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* ...
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*};
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*
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*/
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#include <linux/bcd.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/rtc.h>
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#include <linux/spi/spi.h>
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#include <linux/module.h>
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#include <linux/sysfs.h>
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/* REGISTERS */
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#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
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#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
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#define PCF2123_REG_SC (0x02) /* datetime */
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#define PCF2123_REG_MN (0x03)
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#define PCF2123_REG_HR (0x04)
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#define PCF2123_REG_DM (0x05)
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#define PCF2123_REG_DW (0x06)
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#define PCF2123_REG_MO (0x07)
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#define PCF2123_REG_YR (0x08)
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#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
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#define PCF2123_REG_ALRM_HR (0x0a)
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#define PCF2123_REG_ALRM_DM (0x0b)
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#define PCF2123_REG_ALRM_DW (0x0c)
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#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
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#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
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#define PCF2123_REG_CTDWN_TMR (0x0f)
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/* PCF2123_REG_CTRL1 BITS */
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#define CTRL1_CLEAR (0) /* Clear */
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#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
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#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
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#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
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#define CTRL1_STOP BIT(5) /* Stop the clock */
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#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
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/* PCF2123_REG_CTRL2 BITS */
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#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
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#define CTRL2_AIE BIT(1) /* Alarm irq enable */
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#define CTRL2_TF BIT(2) /* Countdown timer flag */
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#define CTRL2_AF BIT(3) /* Alarm flag */
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#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
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#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
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#define CTRL2_SI BIT(6) /* Second irq enable */
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#define CTRL2_MI BIT(7) /* Minute irq enable */
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/* PCF2123_REG_SC BITS */
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#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
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/* PCF2123_REG_ALRM_XX BITS */
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#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
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/* PCF2123_REG_TMR_CLKOUT BITS */
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#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
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#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
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#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
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#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
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#define CD_TMR_TE BIT(3) /* Countdown timer enable */
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/* PCF2123_REG_OFFSET BITS */
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#define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */
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#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
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#define OFFSET_STEP (2170) /* Offset step in parts per billion */
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/* READ/WRITE ADDRESS BITS */
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#define PCF2123_WRITE BIT(4)
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#define PCF2123_READ (BIT(4) | BIT(7))
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static struct spi_driver pcf2123_driver;
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struct pcf2123_sysfs_reg {
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struct device_attribute attr;
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char name[2];
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};
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struct pcf2123_plat_data {
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struct rtc_device *rtc;
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struct pcf2123_sysfs_reg regs[16];
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};
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/*
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* Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
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* is released properly after an SPI write. This function should be
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* called after EVERY read/write call over SPI.
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*/
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static inline void pcf2123_delay_trec(void)
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{
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ndelay(30);
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}
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static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
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{
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struct spi_device *spi = to_spi_device(dev);
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int ret;
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reg |= PCF2123_READ;
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ret = spi_write_then_read(spi, ®, 1, rxbuf, size);
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pcf2123_delay_trec();
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return ret;
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}
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static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
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{
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struct spi_device *spi = to_spi_device(dev);
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int ret;
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txbuf[0] |= PCF2123_WRITE;
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ret = spi_write(spi, txbuf, size);
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pcf2123_delay_trec();
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return ret;
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}
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static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
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{
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u8 txbuf[2];
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txbuf[0] = reg;
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txbuf[1] = val;
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return pcf2123_write(dev, txbuf, sizeof(txbuf));
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}
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static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
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char *buffer)
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{
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struct pcf2123_sysfs_reg *r;
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u8 rxbuf[1];
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unsigned long reg;
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int ret;
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r = container_of(attr, struct pcf2123_sysfs_reg, attr);
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ret = kstrtoul(r->name, 16, ®);
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if (ret)
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return ret;
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ret = pcf2123_read(dev, reg, rxbuf, 1);
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if (ret < 0)
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return -EIO;
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return sprintf(buffer, "0x%x\n", rxbuf[0]);
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}
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static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
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const char *buffer, size_t count) {
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struct pcf2123_sysfs_reg *r;
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unsigned long reg;
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unsigned long val;
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int ret;
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r = container_of(attr, struct pcf2123_sysfs_reg, attr);
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ret = kstrtoul(r->name, 16, ®);
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if (ret)
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return ret;
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ret = kstrtoul(buffer, 10, &val);
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if (ret)
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return ret;
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pcf2123_write_reg(dev, reg, val);
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if (ret < 0)
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return -EIO;
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return count;
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}
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static int pcf2123_read_offset(struct device *dev, long *offset)
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{
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int ret;
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s8 reg;
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ret = pcf2123_read(dev, PCF2123_REG_OFFSET, ®, 1);
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if (ret < 0)
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return ret;
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if (reg & OFFSET_COARSE)
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reg <<= 1; /* multiply by 2 and sign extend */
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else
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reg |= (reg & OFFSET_SIGN_BIT) << 1; /* sign extend only */
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*offset = ((long)reg) * OFFSET_STEP;
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return 0;
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}
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/*
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* The offset register is a 7 bit signed value with a coarse bit in bit 7.
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* The main difference between the two is normal offset adjusts the first
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* second of n minutes every other hour, with 61, 62 and 63 being shoved
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* into the 60th minute.
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* The coarse adjustment does the same, but every hour.
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* the two overlap, with every even normal offset value corresponding
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* to a coarse offset. Based on this algorithm, it seems that despite the
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* name, coarse offset is a better fit for overlapping values.
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*/
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static int pcf2123_set_offset(struct device *dev, long offset)
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{
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s8 reg;
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if (offset > OFFSET_STEP * 127)
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reg = 127;
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else if (offset < OFFSET_STEP * -128)
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reg = -128;
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else
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reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);
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/* choose fine offset only for odd values in the normal range */
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if (reg & 1 && reg <= 63 && reg >= -64) {
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/* Normal offset. Clear the coarse bit */
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reg &= ~OFFSET_COARSE;
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} else {
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/* Coarse offset. Divide by 2 and set the coarse bit */
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reg >>= 1;
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reg |= OFFSET_COARSE;
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}
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return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
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}
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static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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u8 rxbuf[7];
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int ret;
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ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
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if (ret < 0)
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return ret;
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if (rxbuf[0] & OSC_HAS_STOPPED) {
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dev_info(dev, "clock was stopped. Time is not valid\n");
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return -EINVAL;
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}
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tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
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tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
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tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
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tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
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tm->tm_wday = rxbuf[4] & 0x07;
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tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
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tm->tm_year = bcd2bin(rxbuf[6]);
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if (tm->tm_year < 70)
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tm->tm_year += 100; /* assume we are in 1970...2069 */
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dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
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"mday=%d, mon=%d, year=%d, wday=%d\n",
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__func__,
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tm->tm_sec, tm->tm_min, tm->tm_hour,
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tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
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return rtc_valid_tm(tm);
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}
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static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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u8 txbuf[8];
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int ret;
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dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
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"mday=%d, mon=%d, year=%d, wday=%d\n",
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__func__,
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tm->tm_sec, tm->tm_min, tm->tm_hour,
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tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
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/* Stop the counter first */
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ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
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if (ret < 0)
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return ret;
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/* Set the new time */
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txbuf[0] = PCF2123_REG_SC;
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txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
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txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
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txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
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txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
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txbuf[5] = tm->tm_wday & 0x07;
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txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
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txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
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ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
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if (ret < 0)
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return ret;
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/* Start the counter */
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ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int pcf2123_reset(struct device *dev)
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{
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int ret;
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u8 rxbuf[2];
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ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
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if (ret < 0)
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return ret;
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/* Stop the counter */
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dev_dbg(dev, "stopping RTC\n");
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ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
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if (ret < 0)
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return ret;
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/* See if the counter was actually stopped */
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dev_dbg(dev, "checking for presence of RTC\n");
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ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
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if (ret < 0)
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return ret;
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dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
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rxbuf[0], rxbuf[1]);
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if (!(rxbuf[0] & CTRL1_STOP))
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return -ENODEV;
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/* Start the counter */
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ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
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if (ret < 0)
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return ret;
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return 0;
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}
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static const struct rtc_class_ops pcf2123_rtc_ops = {
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.read_time = pcf2123_rtc_read_time,
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.set_time = pcf2123_rtc_set_time,
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.read_offset = pcf2123_read_offset,
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.set_offset = pcf2123_set_offset,
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};
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static int pcf2123_probe(struct spi_device *spi)
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{
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struct rtc_device *rtc;
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struct rtc_time tm;
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struct pcf2123_plat_data *pdata;
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int ret, i;
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pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
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GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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spi->dev.platform_data = pdata;
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ret = pcf2123_rtc_read_time(&spi->dev, &tm);
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if (ret < 0) {
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ret = pcf2123_reset(&spi->dev);
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if (ret < 0) {
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dev_err(&spi->dev, "chip not found\n");
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goto kfree_exit;
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}
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}
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dev_info(&spi->dev, "spiclk %u KHz.\n",
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(spi->max_speed_hz + 500) / 1000);
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/* Finalize the initialization */
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rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
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&pcf2123_rtc_ops, THIS_MODULE);
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if (IS_ERR(rtc)) {
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dev_err(&spi->dev, "failed to register.\n");
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ret = PTR_ERR(rtc);
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goto kfree_exit;
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}
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pdata->rtc = rtc;
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for (i = 0; i < 16; i++) {
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sysfs_attr_init(&pdata->regs[i].attr.attr);
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sprintf(pdata->regs[i].name, "%1x", i);
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pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
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pdata->regs[i].attr.attr.name = pdata->regs[i].name;
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pdata->regs[i].attr.show = pcf2123_show;
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pdata->regs[i].attr.store = pcf2123_store;
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ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
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if (ret) {
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dev_err(&spi->dev, "Unable to create sysfs %s\n",
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pdata->regs[i].name);
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goto sysfs_exit;
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}
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}
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return 0;
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sysfs_exit:
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for (i--; i >= 0; i--)
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device_remove_file(&spi->dev, &pdata->regs[i].attr);
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kfree_exit:
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spi->dev.platform_data = NULL;
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return ret;
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}
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static int pcf2123_remove(struct spi_device *spi)
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{
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struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
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int i;
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if (pdata) {
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for (i = 0; i < 16; i++)
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if (pdata->regs[i].name[0])
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device_remove_file(&spi->dev,
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&pdata->regs[i].attr);
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}
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return 0;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id pcf2123_dt_ids[] = {
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{ .compatible = "nxp,rtc-pcf2123", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
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#endif
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static struct spi_driver pcf2123_driver = {
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.driver = {
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.name = "rtc-pcf2123",
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.of_match_table = of_match_ptr(pcf2123_dt_ids),
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},
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.probe = pcf2123_probe,
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.remove = pcf2123_remove,
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};
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module_spi_driver(pcf2123_driver);
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MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
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MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
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MODULE_LICENSE("GPL");
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