mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 13:46:47 +07:00
76d7961ff4
- Various switch fall through annotations to fixup warnings & errors
resulting from -Wimplicit-fallthrough.
- A fix for systems (at least jazz) using an i8253 PIT as clocksource
when it's not suitably configured.
- Set struct cacheinfo's cpu_map_populated field to true, indicating
that we filled in cache info detected from cop0 registers & avoiding
complaints about that info being (intentionally) missing in
devicetree.
-----BEGIN PGP SIGNATURE-----
iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCXUnSPBUccGF1bC5idXJ0
b25AbWlwcy5jb20ACgkQPqefrLV1AN2u3gD/TaMPczS5027R0FMXskiroUHaMG4S
JL0EYIVmfny4vwYBAIvLr5l1jEXEqegjYXFabuI5PybQlFmTZMhjauh6gKYJ
=e6fl
-----END PGP SIGNATURE-----
Merge tag 'mips_fixes_5.3_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS fixes from Paul Burton:
"A few MIPS fixes for 5.3:
- Various switch fall through annotations to fixup warnings & errors
resulting from -Wimplicit-fallthrough.
- A fix for systems (at least jazz) using an i8253 PIT as clocksource
when it's not suitably configured.
- Set struct cacheinfo's cpu_map_populated field to true, indicating
that we filled in cache info detected from cop0 registers &
avoiding complaints about that info being (intentionally) missing
in devicetree"
* tag 'mips_fixes_5.3_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: BCM63XX: Mark expected switch fall-through
MIPS: OProfile: Mark expected switch fall-throughs
MIPS: Annotate fall-through in Cavium Octeon code
MIPS: Annotate fall-through in kvm/emulate.c
mips: fix cacheinfo
MIPS: kernel: only use i8253 clocksource with periodic clockevent
79 lines
1.8 KiB
C
79 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* MIPS cacheinfo support
|
|
*/
|
|
#include <linux/cacheinfo.h>
|
|
|
|
/* Populates leaf and increments to next leaf */
|
|
#define populate_cache(cache, leaf, c_level, c_type) \
|
|
do { \
|
|
leaf->type = c_type; \
|
|
leaf->level = c_level; \
|
|
leaf->coherency_line_size = c->cache.linesz; \
|
|
leaf->number_of_sets = c->cache.sets; \
|
|
leaf->ways_of_associativity = c->cache.ways; \
|
|
leaf->size = c->cache.linesz * c->cache.sets * \
|
|
c->cache.ways; \
|
|
leaf++; \
|
|
} while (0)
|
|
|
|
static int __init_cache_level(unsigned int cpu)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
|
int levels = 0, leaves = 0;
|
|
|
|
/*
|
|
* If Dcache is not set, we assume the cache structures
|
|
* are not properly initialized.
|
|
*/
|
|
if (c->dcache.waysize)
|
|
levels += 1;
|
|
else
|
|
return -ENOENT;
|
|
|
|
|
|
leaves += (c->icache.waysize) ? 2 : 1;
|
|
|
|
if (c->scache.waysize) {
|
|
levels++;
|
|
leaves++;
|
|
}
|
|
|
|
if (c->tcache.waysize) {
|
|
levels++;
|
|
leaves++;
|
|
}
|
|
|
|
this_cpu_ci->num_levels = levels;
|
|
this_cpu_ci->num_leaves = leaves;
|
|
return 0;
|
|
}
|
|
|
|
static int __populate_cache_leaves(unsigned int cpu)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
|
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
|
|
|
|
if (c->icache.waysize) {
|
|
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
|
|
populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
|
|
} else {
|
|
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
|
|
}
|
|
|
|
if (c->scache.waysize)
|
|
populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
|
|
|
|
if (c->tcache.waysize)
|
|
populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
|
|
|
|
this_cpu_ci->cpu_map_populated = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
|
|
DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)
|