mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
11027ce6f1
Defines for some RTC related registers were missing, also they were not included in the volatile register list Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Lee Jones <lee.jones@linaro.org>
277 lines
7.6 KiB
C
277 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* MFD core driver for Ricoh RN5T618 PMIC
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*/
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#ifndef __LINUX_MFD_RN5T618_H
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#define __LINUX_MFD_RN5T618_H
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#include <linux/regmap.h>
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#define RN5T618_LSIVER 0x00
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#define RN5T618_OTPVER 0x01
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#define RN5T618_IODAC 0x02
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#define RN5T618_VINDAC 0x03
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#define RN5T618_OUT32KEN 0x05
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#define RN5T618_CPUCNT 0x06
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#define RN5T618_PSWR 0x07
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#define RN5T618_PONHIS 0x09
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#define RN5T618_POFFHIS 0x0a
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#define RN5T618_WATCHDOG 0x0b
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#define RN5T618_WATCHDOGCNT 0x0c
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#define RN5T618_PWRFUNC 0x0d
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#define RN5T618_SLPCNT 0x0e
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#define RN5T618_REPCNT 0x0f
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#define RN5T618_PWRONTIMSET 0x10
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#define RN5T618_NOETIMSETCNT 0x11
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#define RN5T618_PWRIREN 0x12
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#define RN5T618_PWRIRQ 0x13
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#define RN5T618_PWRMON 0x14
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#define RN5T618_PWRIRSEL 0x15
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#define RN5T618_DC1_SLOT 0x16
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#define RN5T618_DC2_SLOT 0x17
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#define RN5T618_DC3_SLOT 0x18
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#define RN5T618_DC4_SLOT 0x19
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#define RN5T618_LDO1_SLOT 0x1b
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#define RN5T618_LDO2_SLOT 0x1c
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#define RN5T618_LDO3_SLOT 0x1d
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#define RN5T618_LDO4_SLOT 0x1e
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#define RN5T618_LDO5_SLOT 0x1f
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#define RN5T618_PSO0_SLOT 0x25
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#define RN5T618_PSO1_SLOT 0x26
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#define RN5T618_PSO2_SLOT 0x27
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#define RN5T618_PSO3_SLOT 0x28
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#define RN5T618_LDORTC1_SLOT 0x2a
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#define RN5T618_DC1CTL 0x2c
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#define RN5T618_DC1CTL2 0x2d
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#define RN5T618_DC2CTL 0x2e
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#define RN5T618_DC2CTL2 0x2f
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#define RN5T618_DC3CTL 0x30
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#define RN5T618_DC3CTL2 0x31
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#define RN5T618_DC4CTL 0x32
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#define RN5T618_DC4CTL2 0x33
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#define RN5T618_DC5CTL 0x34
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#define RN5T618_DC5CTL2 0x35
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#define RN5T618_DC1DAC 0x36
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#define RN5T618_DC2DAC 0x37
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#define RN5T618_DC3DAC 0x38
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#define RN5T618_DC4DAC 0x39
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#define RN5T618_DC5DAC 0x3a
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#define RN5T618_DC1DAC_SLP 0x3b
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#define RN5T618_DC2DAC_SLP 0x3c
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#define RN5T618_DC3DAC_SLP 0x3d
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#define RN5T618_DC4DAC_SLP 0x3e
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#define RN5T618_DCIREN 0x40
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#define RN5T618_DCIRQ 0x41
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#define RN5T618_DCIRMON 0x42
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#define RN5T618_LDOEN1 0x44
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#define RN5T618_LDOEN2 0x45
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#define RN5T618_LDODIS 0x46
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#define RN5T618_LDO1DAC 0x4c
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#define RN5T618_LDO2DAC 0x4d
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#define RN5T618_LDO3DAC 0x4e
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#define RN5T618_LDO4DAC 0x4f
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#define RN5T618_LDO5DAC 0x50
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#define RN5T618_LDO6DAC 0x51
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#define RN5T618_LDO7DAC 0x52
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#define RN5T618_LDO8DAC 0x53
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#define RN5T618_LDO9DAC 0x54
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#define RN5T618_LDO10DAC 0x55
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#define RN5T618_LDORTCDAC 0x56
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#define RN5T618_LDORTC2DAC 0x57
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#define RN5T618_LDO1DAC_SLP 0x58
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#define RN5T618_LDO2DAC_SLP 0x59
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#define RN5T618_LDO3DAC_SLP 0x5a
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#define RN5T618_LDO4DAC_SLP 0x5b
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#define RN5T618_LDO5DAC_SLP 0x5c
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#define RN5T618_ADCCNT1 0x64
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#define RN5T618_ADCCNT2 0x65
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#define RN5T618_ADCCNT3 0x66
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#define RN5T618_ILIMDATAH 0x68
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#define RN5T618_ILIMDATAL 0x69
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#define RN5T618_VBATDATAH 0x6a
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#define RN5T618_VBATDATAL 0x6b
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#define RN5T618_VADPDATAH 0x6c
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#define RN5T618_VADPDATAL 0x6d
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#define RN5T618_VUSBDATAH 0x6e
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#define RN5T618_VUSBDATAL 0x6f
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#define RN5T618_VSYSDATAH 0x70
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#define RN5T618_VSYSDATAL 0x71
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#define RN5T618_VTHMDATAH 0x72
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#define RN5T618_VTHMDATAL 0x73
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#define RN5T618_AIN1DATAH 0x74
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#define RN5T618_AIN1DATAL 0x75
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#define RN5T618_AIN0DATAH 0x76
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#define RN5T618_AIN0DATAL 0x77
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#define RN5T618_ILIMTHL 0x78
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#define RN5T618_ILIMTHH 0x79
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#define RN5T618_VBATTHL 0x7a
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#define RN5T618_VBATTHH 0x7b
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#define RN5T618_VADPTHL 0x7c
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#define RN5T618_VADPTHH 0x7d
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#define RN5T618_VUSBTHL 0x7e
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#define RN5T618_VUSBTHH 0x7f
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#define RN5T618_VSYSTHL 0x80
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#define RN5T618_VSYSTHH 0x81
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#define RN5T618_VTHMTHL 0x82
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#define RN5T618_VTHMTHH 0x83
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#define RN5T618_AIN1THL 0x84
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#define RN5T618_AIN1THH 0x85
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#define RN5T618_AIN0THL 0x86
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#define RN5T618_AIN0THH 0x87
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#define RN5T618_EN_ADCIR1 0x88
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#define RN5T618_EN_ADCIR2 0x89
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#define RN5T618_EN_ADCIR3 0x8a
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#define RN5T618_IR_ADC1 0x8c
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#define RN5T618_IR_ADC2 0x8d
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#define RN5T618_IR_ADC3 0x8e
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#define RN5T618_IOSEL 0x90
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#define RN5T618_IOOUT 0x91
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#define RN5T618_GPEDGE1 0x92
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#define RN5T618_GPEDGE2 0x93
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#define RN5T618_EN_GPIR 0x94
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#define RN5T618_IR_GPR 0x95
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#define RN5T618_IR_GPF 0x96
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#define RN5T618_MON_IOIN 0x97
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#define RN5T618_GPLED_FUNC 0x98
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#define RN5T618_INTPOL 0x9c
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#define RN5T618_INTEN 0x9d
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#define RN5T618_INTMON 0x9e
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#define RN5T618_RTC_SECONDS 0xA0
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#define RN5T618_RTC_MDAY 0xA4
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#define RN5T618_RTC_MONTH 0xA5
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#define RN5T618_RTC_YEAR 0xA6
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#define RN5T618_RTC_ADJUST 0xA7
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#define RN5T618_RTC_ALARM_Y_SEC 0xA8
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#define RN5T618_RTC_DAL_MONTH 0xAC
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#define RN5T618_RTC_CTRL1 0xAE
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#define RN5T618_RTC_CTRL2 0xAF
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#define RN5T618_PREVINDAC 0xb0
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#define RN5T618_BATDAC 0xb1
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#define RN5T618_CHGCTL1 0xb3
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#define RN5T618_CHGCTL2 0xb4
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#define RN5T618_VSYSSET 0xb5
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#define RN5T618_REGISET1 0xb6
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#define RN5T618_REGISET2 0xb7
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#define RN5T618_CHGISET 0xb8
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#define RN5T618_TIMSET 0xb9
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#define RN5T618_BATSET1 0xba
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#define RN5T618_BATSET2 0xbb
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#define RN5T618_DIESET 0xbc
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#define RN5T618_CHGSTATE 0xbd
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#define RN5T618_CHGCTRL_IRFMASK 0xbe
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#define RN5T618_CHGSTAT_IRFMASK1 0xbf
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#define RN5T618_CHGSTAT_IRFMASK2 0xc0
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#define RN5T618_CHGERR_IRFMASK 0xc1
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#define RN5T618_CHGCTRL_IRR 0xc2
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#define RN5T618_CHGSTAT_IRR1 0xc3
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#define RN5T618_CHGSTAT_IRR2 0xc4
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#define RN5T618_CHGERR_IRR 0xc5
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#define RN5T618_CHGCTRL_MONI 0xc6
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#define RN5T618_CHGSTAT_MONI1 0xc7
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#define RN5T618_CHGSTAT_MONI2 0xc8
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#define RN5T618_CHGERR_MONI 0xc9
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#define RN5T618_CHGCTRL_DETMOD1 0xca
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#define RN5T618_CHGCTRL_DETMOD2 0xcb
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#define RN5T618_CHGSTAT_DETMOD1 0xcc
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#define RN5T618_CHGSTAT_DETMOD2 0xcd
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#define RN5T618_CHGSTAT_DETMOD3 0xce
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#define RN5T618_CHGERR_DETMOD1 0xcf
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#define RN5T618_CHGERR_DETMOD2 0xd0
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#define RN5T618_CHGOSCCTL 0xd4
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#define RN5T618_CHGOSCSCORESET1 0xd5
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#define RN5T618_CHGOSCSCORESET2 0xd6
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#define RN5T618_CHGOSCSCORESET3 0xd7
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#define RN5T618_CHGOSCFREQSET1 0xd8
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#define RN5T618_CHGOSCFREQSET2 0xd9
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#define RN5T618_CONTROL 0xe0
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#define RN5T618_SOC 0xe1
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#define RN5T618_RE_CAP_H 0xe2
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#define RN5T618_RE_CAP_L 0xe3
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#define RN5T618_FA_CAP_H 0xe4
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#define RN5T618_FA_CAP_L 0xe5
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#define RN5T618_AGE 0xe6
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#define RN5T618_TT_EMPTY_H 0xe7
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#define RN5T618_TT_EMPTY_L 0xe8
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#define RN5T618_TT_FULL_H 0xe9
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#define RN5T618_TT_FULL_L 0xea
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#define RN5T618_VOLTAGE_1 0xeb
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#define RN5T618_VOLTAGE_0 0xec
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#define RN5T618_TEMP_1 0xed
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#define RN5T618_TEMP_0 0xee
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#define RN5T618_CC_CTRL 0xef
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#define RN5T618_CC_COUNT2 0xf0
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#define RN5T618_CC_COUNT1 0xf1
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#define RN5T618_CC_COUNT0 0xf2
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#define RN5T618_CC_SUMREG3 0xf3
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#define RN5T618_CC_SUMREG2 0xf4
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#define RN5T618_CC_SUMREG1 0xf5
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#define RN5T618_CC_SUMREG0 0xf6
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#define RN5T618_CC_OFFREG1 0xf7
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#define RN5T618_CC_OFFREG0 0xf8
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#define RN5T618_CC_GAINREG1 0xf9
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#define RN5T618_CC_GAINREG0 0xfa
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#define RN5T618_CC_AVEREG1 0xfb
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#define RN5T618_CC_AVEREG0 0xfc
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#define RN5T618_MAX_REG 0xfc
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#define RN5T618_REPCNT_REPWRON BIT(0)
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#define RN5T618_SLPCNT_SWPWROFF BIT(0)
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#define RN5T618_WATCHDOG_WDOGEN BIT(2)
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#define RN5T618_WATCHDOG_WDOGTIM_M (BIT(0) | BIT(1))
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#define RN5T618_WATCHDOG_WDOGTIM_S 0
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#define RN5T618_PWRIRQ_IR_WDOG BIT(6)
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enum {
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RN5T618_DCDC1,
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RN5T618_DCDC2,
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RN5T618_DCDC3,
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RN5T618_DCDC4,
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RN5T618_DCDC5,
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RN5T618_LDO1,
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RN5T618_LDO2,
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RN5T618_LDO3,
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RN5T618_LDO4,
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RN5T618_LDO5,
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RN5T618_LDO6,
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RN5T618_LDO7,
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RN5T618_LDO8,
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RN5T618_LDO9,
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RN5T618_LDO10,
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RN5T618_LDORTC1,
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RN5T618_LDORTC2,
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RN5T618_REG_NUM,
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};
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enum {
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RN5T567 = 0,
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RN5T618,
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RC5T619,
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};
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/* RN5T618 IRQ definitions */
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enum {
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RN5T618_IRQ_SYS = 0,
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RN5T618_IRQ_DCDC,
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RN5T618_IRQ_RTC,
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RN5T618_IRQ_ADC,
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RN5T618_IRQ_GPIO,
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RN5T618_IRQ_CHG,
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RN5T618_NR_IRQS,
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};
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struct rn5t618 {
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struct regmap *regmap;
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struct device *dev;
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long variant;
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int irq;
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struct regmap_irq_chip_data *irq_data;
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};
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#endif /* __LINUX_MFD_RN5T618_H */
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