mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 02:16:43 +07:00
119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
/*
|
|
* Copyright 2001 MontaVista Software Inc.
|
|
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
|
|
*
|
|
* Copyright (C) 2001 Ralf Baechle
|
|
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
|
|
* Author: Maciej W. Rozycki <macro@mips.com>
|
|
*
|
|
* This file define the irq handler for MIPS CPU interrupts.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/*
|
|
* Almost all MIPS CPUs define 8 interrupt sources. They are typically
|
|
* level triggered (i.e., cannot be cleared from CPU; must be cleared from
|
|
* device). The first two are software interrupts which we don't really
|
|
* use or support. The last one is usually the CPU timer interrupt if
|
|
* counter register is present or, for CPUs with an external FPU, by
|
|
* convention it's the FPU exception interrupt.
|
|
*
|
|
* Don't even think about using this on SMP. You have been warned.
|
|
*
|
|
* This file exports one global function:
|
|
* void mips_cpu_irq_init(void);
|
|
*/
|
|
#include <linux/init.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/irq.h>
|
|
|
|
#include <asm/irq_cpu.h>
|
|
#include <asm/mipsregs.h>
|
|
#include <asm/mipsmtregs.h>
|
|
#include <asm/system.h>
|
|
|
|
static inline void unmask_mips_irq(struct irq_data *d)
|
|
{
|
|
set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
|
|
irq_enable_hazard();
|
|
}
|
|
|
|
static inline void mask_mips_irq(struct irq_data *d)
|
|
{
|
|
clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
|
|
irq_disable_hazard();
|
|
}
|
|
|
|
static struct irq_chip mips_cpu_irq_controller = {
|
|
.name = "MIPS",
|
|
.irq_ack = mask_mips_irq,
|
|
.irq_mask = mask_mips_irq,
|
|
.irq_mask_ack = mask_mips_irq,
|
|
.irq_unmask = unmask_mips_irq,
|
|
.irq_eoi = unmask_mips_irq,
|
|
};
|
|
|
|
/*
|
|
* Basically the same as above but taking care of all the MT stuff
|
|
*/
|
|
|
|
static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
|
|
{
|
|
unsigned int vpflags = dvpe();
|
|
|
|
clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
|
|
evpe(vpflags);
|
|
unmask_mips_irq(d);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* While we ack the interrupt interrupts are disabled and thus we don't need
|
|
* to deal with concurrency issues. Same for mips_cpu_irq_end.
|
|
*/
|
|
static void mips_mt_cpu_irq_ack(struct irq_data *d)
|
|
{
|
|
unsigned int vpflags = dvpe();
|
|
clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
|
|
evpe(vpflags);
|
|
mask_mips_irq(d);
|
|
}
|
|
|
|
static struct irq_chip mips_mt_cpu_irq_controller = {
|
|
.name = "MIPS",
|
|
.irq_startup = mips_mt_cpu_irq_startup,
|
|
.irq_ack = mips_mt_cpu_irq_ack,
|
|
.irq_mask = mask_mips_irq,
|
|
.irq_mask_ack = mips_mt_cpu_irq_ack,
|
|
.irq_unmask = unmask_mips_irq,
|
|
.irq_eoi = unmask_mips_irq,
|
|
};
|
|
|
|
void __init mips_cpu_irq_init(void)
|
|
{
|
|
int irq_base = MIPS_CPU_IRQ_BASE;
|
|
int i;
|
|
|
|
/* Mask interrupts. */
|
|
clear_c0_status(ST0_IM);
|
|
clear_c0_cause(CAUSEF_IP);
|
|
|
|
/*
|
|
* Only MT is using the software interrupts currently, so we just
|
|
* leave them uninitialized for other processors.
|
|
*/
|
|
if (cpu_has_mipsmt)
|
|
for (i = irq_base; i < irq_base + 2; i++)
|
|
irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,
|
|
handle_percpu_irq);
|
|
|
|
for (i = irq_base + 2; i < irq_base + 8; i++)
|
|
irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
|
|
handle_percpu_irq);
|
|
}
|