Mikko Perttunen 4ac45eb8d1 gpu: host1x: Fix bitshift/mask multipliers ... Some parts of Host1x uses BIT_WORD/BIT_MASK/BITS_PER_LONG to calculate register or field offsets. This worked fine on ARMv7, but now that BITS_PER_LONG is 64 but our registers are still 32-bit things are broken. Fix by replacing.. - BIT_WORD with (x / 32) - BIT_MASK with BIT(x % 32) - BITS_PER_LONG with 32 Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2017-08-17 17:57:06 +02:00
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cdma_hw.c	gpu: host1x: Add IOMMU support	2017-04-05 18:11:43 +02:00
channel_hw.c	gpu: host1x: Refactor channel allocation code	2017-06-15 14:25:38 +02:00
debug_hw.c	gpu: host1x: Whitespace cleanup for readability	2016-06-23 11:59:30 +02:00
host1x01_hardware.h
host1x01.c
host1x01.h
host1x02_hardware.h
host1x02.c
host1x02.h
host1x04_hardware.h
host1x04.c
host1x04.h
host1x05_hardware.h
host1x05.c
host1x05.h
hw_host1x01_channel.h
hw_host1x01_sync.h
hw_host1x01_uclass.h
hw_host1x02_channel.h
hw_host1x02_sync.h
hw_host1x02_uclass.h
hw_host1x04_channel.h
hw_host1x04_sync.h
hw_host1x04_uclass.h
hw_host1x05_channel.h
hw_host1x05_sync.h
hw_host1x05_uclass.h
intr_hw.c	gpu: host1x: Fix bitshift/mask multipliers	2017-08-17 17:57:06 +02:00
syncpt_hw.c	gpu: host1x: Fix bitshift/mask multipliers	2017-08-17 17:57:06 +02:00