mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 07:07:40 +07:00
9e1ac462b9
Commit63288b721a("ARM: imx: fix shared gate clock") attempted to fix an issue with particular enable/disable sequence from two shared gate clocks. But unfortunately, while it partially fixed the issue, it also did something wrong in .is_enabled() function hook. In case of shared gate, the function shouldn't really query the hardware state via share_count, because the function is trying to query the enabling state of the clock in question, not the hardware state which is shared by multiple clocks. Fix the issue by returning the enable_count of the clock itself which is maintained by clock core, in case it's a clock sharing hardware gate with others. As the result, the initialization of share_count per hardware state is not needed now. So remove it. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes:63288b721a("ARM: imx: fix shared gate clock") Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
146 lines
3.2 KiB
C
146 lines
3.2 KiB
C
/*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Gated clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include "clk.h"
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/**
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* DOC: basic gatable clock which can gate and ungate it's ouput
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable and clk_disable are functional & control gating
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* rate - inherits rate from parent. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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struct clk_gate2 {
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struct clk_hw hw;
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void __iomem *reg;
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u8 bit_idx;
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u8 flags;
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spinlock_t *lock;
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unsigned int *share_count;
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};
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#define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
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static int clk_gate2_enable(struct clk_hw *hw)
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{
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struct clk_gate2 *gate = to_clk_gate2(hw);
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u32 reg;
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unsigned long flags = 0;
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spin_lock_irqsave(gate->lock, flags);
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if (gate->share_count && (*gate->share_count)++ > 0)
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goto out;
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reg = readl(gate->reg);
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reg |= 3 << gate->bit_idx;
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writel(reg, gate->reg);
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out:
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spin_unlock_irqrestore(gate->lock, flags);
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return 0;
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}
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static void clk_gate2_disable(struct clk_hw *hw)
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{
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struct clk_gate2 *gate = to_clk_gate2(hw);
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u32 reg;
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unsigned long flags = 0;
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spin_lock_irqsave(gate->lock, flags);
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if (gate->share_count) {
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if (WARN_ON(*gate->share_count == 0))
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goto out;
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else if (--(*gate->share_count) > 0)
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goto out;
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}
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reg = readl(gate->reg);
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reg &= ~(3 << gate->bit_idx);
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writel(reg, gate->reg);
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out:
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
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{
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u32 val = readl(reg);
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if (((val >> bit_idx) & 1) == 1)
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return 1;
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return 0;
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}
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static int clk_gate2_is_enabled(struct clk_hw *hw)
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{
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struct clk_gate2 *gate = to_clk_gate2(hw);
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if (gate->share_count)
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return !!__clk_get_enable_count(hw->clk);
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else
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return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
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}
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static struct clk_ops clk_gate2_ops = {
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.enable = clk_gate2_enable,
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.disable = clk_gate2_disable,
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.is_enabled = clk_gate2_is_enabled,
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};
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate2_flags, spinlock_t *lock,
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unsigned int *share_count)
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{
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struct clk_gate2 *gate;
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struct clk *clk;
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struct clk_init_data init;
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gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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/* struct clk_gate2 assignments */
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gate->reg = reg;
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gate->bit_idx = bit_idx;
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gate->flags = clk_gate2_flags;
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gate->lock = lock;
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gate->share_count = share_count;
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init.name = name;
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init.ops = &clk_gate2_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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gate->hw.init = &init;
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clk = clk_register(dev, &gate->hw);
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if (IS_ERR(clk))
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kfree(gate);
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return clk;
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}
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