Guo Ren 761b4f694c csky: Support icache flush without specific instructions ... Some CPUs don't support icache specific instructions to flush icache lines in broadcast way. We use cpu control registers to flush local icache and use IPI to notify other cores. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>		2020-02-21 15:43:24 +08:00
..
asid.c	csky: Add new asid lib code from arm	2019-07-19 14:21:36 +08:00
cachev1.c	csky: Support icache flush without specific instructions	2020-02-21 15:43:24 +08:00
cachev2.c	csky: Support icache flush without specific instructions	2020-02-21 15:43:24 +08:00
context.c	csky: Use generic asid algorithm to implement switch_mm	2019-07-19 14:21:36 +08:00
dma-mapping.c	dma-mapping: drop the dev argument to arch_sync_dma_for_*	2019-11-20 20:31:38 +01:00
fault.c	signal: Remove the task parameter from force_sig_fault	2019-05-29 09:31:43 -05:00
highmem.c	csky: Separate fixaddr_init from highmem	2020-02-21 15:43:24 +08:00
init.c	csky/mm: Fixup export invalid_pte_table symbol	2020-02-21 15:43:24 +08:00
ioremap.c	csky: use generic ioremap	2019-11-12 11:37:52 +01:00
Makefile	csky: Tightly-Coupled Memory or Sram support	2020-02-21 15:43:24 +08:00
syscache.c	csky: Cache and TLB routines	2018-10-25 23:36:19 +08:00
tcm.c	csky: Tightly-Coupled Memory or Sram support	2020-02-21 15:43:24 +08:00
tlb.c	csky: Improve tlb operation with help of asid	2019-07-19 14:21:36 +08:00