Krish Sadhukhan 5866e9205b x86/cpu: Add hardware-enforced cache coherency as a CPUID feature ... In some hardware implementations, coherency between the encrypted and unencrypted mappings of the same physical page is enforced. In such a system, it is not required for software to flush the page from all CPU caches in the system prior to changing the value of the C-bit for a page. This hardware- enforced cache coherency is indicated by EAX[10] in CPUID leaf 0x8000001f. [ bp: Use one of the free slots in word 3. ] Suggested-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/20200917212038.5090-2-krish.sadhukhan@oracle.com		2020-09-18 10:46:41 +02:00
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asm	x86/cpu: Add hardware-enforced cache coherency as a CPUID feature	2020-09-18 10:46:41 +02:00
uapi/asm	Support for FSGSBASE. Almost 5 years after the first RFC to support it,	2020-08-04 21:16:22 -07:00