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c362b2f34e
This work implements jiting of BPF_J{LT,LE,SLT,SLE} instructions
with BPF_X/BPF_K variants for the arm64 eBPF JIT.
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
203 lines
8.4 KiB
C
203 lines
8.4 KiB
C
/*
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* BPF JIT compiler for ARM64
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*
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* Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BPF_JIT_H
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#define _BPF_JIT_H
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#include <asm/insn.h>
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/* 5-bit Register Operand */
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#define A64_R(x) AARCH64_INSN_REG_##x
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#define A64_FP AARCH64_INSN_REG_FP
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#define A64_LR AARCH64_INSN_REG_LR
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#define A64_ZR AARCH64_INSN_REG_ZR
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#define A64_SP AARCH64_INSN_REG_SP
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#define A64_VARIANT(sf) \
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((sf) ? AARCH64_INSN_VARIANT_64BIT : AARCH64_INSN_VARIANT_32BIT)
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/* Compare & branch (immediate) */
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#define A64_COMP_BRANCH(sf, Rt, offset, type) \
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aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \
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AARCH64_INSN_BRANCH_COMP_##type)
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#define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO)
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#define A64_CBNZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, NONZERO)
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/* Conditional branch (immediate) */
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#define A64_COND_BRANCH(cond, offset) \
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aarch64_insn_gen_cond_branch_imm(0, offset, cond)
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#define A64_COND_EQ AARCH64_INSN_COND_EQ /* == */
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#define A64_COND_NE AARCH64_INSN_COND_NE /* != */
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#define A64_COND_CS AARCH64_INSN_COND_CS /* unsigned >= */
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#define A64_COND_HI AARCH64_INSN_COND_HI /* unsigned > */
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#define A64_COND_LS AARCH64_INSN_COND_LS /* unsigned <= */
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#define A64_COND_CC AARCH64_INSN_COND_CC /* unsigned < */
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#define A64_COND_GE AARCH64_INSN_COND_GE /* signed >= */
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#define A64_COND_GT AARCH64_INSN_COND_GT /* signed > */
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#define A64_COND_LE AARCH64_INSN_COND_LE /* signed <= */
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#define A64_COND_LT AARCH64_INSN_COND_LT /* signed < */
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#define A64_B_(cond, imm19) A64_COND_BRANCH(cond, (imm19) << 2)
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/* Unconditional branch (immediate) */
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#define A64_BRANCH(offset, type) aarch64_insn_gen_branch_imm(0, offset, \
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AARCH64_INSN_BRANCH_##type)
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#define A64_B(imm26) A64_BRANCH((imm26) << 2, NOLINK)
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#define A64_BL(imm26) A64_BRANCH((imm26) << 2, LINK)
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/* Unconditional branch (register) */
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#define A64_BR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_NOLINK)
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#define A64_BLR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_LINK)
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#define A64_RET(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_RETURN)
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/* Load/store register (register offset) */
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#define A64_LS_REG(Rt, Rn, Rm, size, type) \
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aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
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AARCH64_INSN_SIZE_##size, \
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AARCH64_INSN_LDST_##type##_REG_OFFSET)
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#define A64_STRB(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 8, STORE)
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#define A64_LDRB(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 8, LOAD)
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#define A64_STRH(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 16, STORE)
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#define A64_LDRH(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 16, LOAD)
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#define A64_STR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, STORE)
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#define A64_LDR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, LOAD)
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#define A64_STR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, STORE)
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#define A64_LDR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, LOAD)
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/* Load/store register pair */
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#define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \
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aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \
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AARCH64_INSN_VARIANT_64BIT, \
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AARCH64_INSN_LDST_##ls##_PAIR_##type)
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/* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */
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#define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX)
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/* Rt = Rn[0]; Rt2 = Rn[8]; Rn += 16; */
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#define A64_POP(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)
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/* Load/store exclusive */
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#define A64_SIZE(sf) \
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((sf) ? AARCH64_INSN_SIZE_64 : AARCH64_INSN_SIZE_32)
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#define A64_LSX(sf, Rt, Rn, Rs, type) \
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aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
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AARCH64_INSN_LDST_##type)
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/* Rt = [Rn]; (atomic) */
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#define A64_LDXR(sf, Rt, Rn) \
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A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX)
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/* [Rn] = Rt; (atomic) Rs = [state] */
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#define A64_STXR(sf, Rt, Rn, Rs) \
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A64_LSX(sf, Rt, Rn, Rs, STORE_EX)
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/* Prefetch */
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#define A64_PRFM(Rn, type, target, policy) \
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aarch64_insn_gen_prefetch(Rn, AARCH64_INSN_PRFM_TYPE_##type, \
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AARCH64_INSN_PRFM_TARGET_##target, \
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AARCH64_INSN_PRFM_POLICY_##policy)
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/* Add/subtract (immediate) */
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#define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \
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aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
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A64_VARIANT(sf), AARCH64_INSN_ADSB_##type)
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/* Rd = Rn OP imm12 */
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#define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
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#define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB)
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/* Rd = Rn */
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#define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0)
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/* Bitfield move */
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#define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \
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aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
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A64_VARIANT(sf), AARCH64_INSN_BITFIELD_MOVE_##type)
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/* Signed, with sign replication to left and zeros to right */
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#define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED)
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/* Unsigned, with zeros to left and right */
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#define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED)
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/* Rd = Rn << shift */
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#define A64_LSL(sf, Rd, Rn, shift) ({ \
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int sz = (sf) ? 64 : 32; \
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A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \
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})
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/* Rd = Rn >> shift */
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#define A64_LSR(sf, Rd, Rn, shift) A64_UBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
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/* Rd = Rn >> shift; signed */
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#define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
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/* Zero extend */
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#define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15)
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#define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31)
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/* Move wide (immediate) */
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#define A64_MOVEW(sf, Rd, imm16, shift, type) \
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aarch64_insn_gen_movewide(Rd, imm16, shift, \
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A64_VARIANT(sf), AARCH64_INSN_MOVEWIDE_##type)
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/* Rd = Zeros (for MOVZ);
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* Rd |= imm16 << shift (where shift is {0, 16, 32, 48});
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* Rd = ~Rd; (for MOVN); */
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#define A64_MOVN(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, INVERSE)
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#define A64_MOVZ(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, ZERO)
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#define A64_MOVK(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, KEEP)
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/* Add/subtract (shifted register) */
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#define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \
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aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
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A64_VARIANT(sf), AARCH64_INSN_ADSB_##type)
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/* Rd = Rn OP Rm */
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#define A64_ADD(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
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#define A64_SUB(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)
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#define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)
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/* Rd = -Rm */
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#define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)
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/* Rn - Rm; set condition flags */
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#define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)
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/* Data-processing (1 source) */
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#define A64_DATA1(sf, Rd, Rn, type) aarch64_insn_gen_data1(Rd, Rn, \
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A64_VARIANT(sf), AARCH64_INSN_DATA1_##type)
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/* Rd = BSWAPx(Rn) */
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#define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16)
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#define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32)
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#define A64_REV64(Rd, Rn) A64_DATA1(1, Rd, Rn, REVERSE_64)
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/* Data-processing (2 source) */
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/* Rd = Rn OP Rm */
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#define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \
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A64_VARIANT(sf), AARCH64_INSN_DATA2_##type)
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#define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)
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#define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)
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#define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)
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#define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)
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/* Data-processing (3 source) */
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/* Rd = Ra + Rn * Rm */
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#define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
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A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD)
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/* Rd = Rn * Rm */
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#define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
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/* Logical (shifted register) */
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#define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \
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aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
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A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
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/* Rd = Rn OP Rm */
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#define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
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#define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
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#define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
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#define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)
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/* Rn & Rm; set condition flags */
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#define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
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#endif /* _BPF_JIT_H */
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