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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7573afdf80
The functions are used for devices with memory mapped I/O and contain no PCI specific code at all. Use rt2800mmio prefix instead of rt2800pci in the function names to reflect that. The patch contains no functional changes. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
748 lines
21 KiB
C
748 lines
21 KiB
C
/*
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Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
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Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
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Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
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Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
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Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
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Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
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Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
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Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the
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Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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Module: rt2800pci
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Abstract: rt2800pci device specific routines.
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Supported chipsets: RT2800E & RT2800ED.
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*/
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/eeprom_93cx6.h>
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#include "rt2x00.h"
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#include "rt2x00mmio.h"
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#include "rt2x00pci.h"
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#include "rt2x00soc.h"
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#include "rt2800lib.h"
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#include "rt2800mmio.h"
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#include "rt2800.h"
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#include "rt2800pci.h"
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/*
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* Allow hardware encryption to be disabled.
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*/
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static bool modparam_nohwcrypt = false;
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module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
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MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
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static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
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{
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return modparam_nohwcrypt;
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}
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static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
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{
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unsigned int i;
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u32 reg;
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/*
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* SOC devices don't support MCU requests.
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*/
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if (rt2x00_is_soc(rt2x00dev))
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return;
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for (i = 0; i < 200; i++) {
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rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
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if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
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(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
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(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
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(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
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break;
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udelay(REGISTER_BUSY_DELAY);
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}
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if (i == 200)
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rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
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}
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#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
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static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
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{
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void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
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if (!base_addr)
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return -ENOMEM;
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memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
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iounmap(base_addr);
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return 0;
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}
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#else
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static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
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{
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return -ENOMEM;
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}
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#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
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#ifdef CONFIG_PCI
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static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
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{
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg;
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rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®);
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eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
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eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
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eeprom->reg_data_clock =
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!!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
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eeprom->reg_chip_select =
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!!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
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}
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static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
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{
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg = 0;
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rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
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rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
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rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
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!!eeprom->reg_data_clock);
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rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
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!!eeprom->reg_chip_select);
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rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
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}
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static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
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{
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struct eeprom_93cx6 eeprom;
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u32 reg;
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rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®);
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eeprom.data = rt2x00dev;
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eeprom.register_read = rt2800pci_eepromregister_read;
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eeprom.register_write = rt2800pci_eepromregister_write;
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switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
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{
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case 0:
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eeprom.width = PCI_EEPROM_WIDTH_93C46;
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break;
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case 1:
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eeprom.width = PCI_EEPROM_WIDTH_93C66;
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break;
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default:
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eeprom.width = PCI_EEPROM_WIDTH_93C86;
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break;
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}
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eeprom.reg_data_in = 0;
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eeprom.reg_data_out = 0;
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eeprom.reg_data_clock = 0;
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eeprom.reg_chip_select = 0;
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eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
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EEPROM_SIZE / sizeof(u16));
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return 0;
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}
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static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
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{
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return rt2800_efuse_detect(rt2x00dev);
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}
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static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
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{
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return rt2800_read_eeprom_efuse(rt2x00dev);
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}
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#else
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static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
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{
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return -EOPNOTSUPP;
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}
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static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
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{
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return 0;
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}
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static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
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{
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return -EOPNOTSUPP;
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}
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#endif /* CONFIG_PCI */
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/*
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* Firmware functions
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*/
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static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
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{
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/*
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* Chip rt3290 use specific 4KB firmware named rt3290.bin.
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*/
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if (rt2x00_rt(rt2x00dev, RT3290))
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return FIRMWARE_RT3290;
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else
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return FIRMWARE_RT2860;
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}
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static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
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const u8 *data, const size_t len)
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{
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u32 reg;
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/*
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* enable Host program ram write selection
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*/
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reg = 0;
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rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
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/*
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* Write firmware to device.
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*/
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rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
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data, len);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
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rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
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return 0;
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}
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/*
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* Initialization functions.
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*/
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static bool rt2800mmio_get_entry_state(struct queue_entry *entry)
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{
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struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
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u32 word;
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if (entry->queue->qid == QID_RX) {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
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} else {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
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}
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}
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static void rt2800mmio_clear_entry(struct queue_entry *entry)
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{
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struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
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struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
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struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
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u32 word;
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if (entry->queue->qid == QID_RX) {
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rt2x00_desc_read(entry_priv->desc, 0, &word);
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rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
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rt2x00_desc_write(entry_priv->desc, 0, word);
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
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rt2x00_desc_write(entry_priv->desc, 1, word);
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/*
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* Set RX IDX in register to inform hardware that we have
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* handled this entry and it is available for reuse again.
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*/
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rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
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entry->entry_idx);
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} else {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
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rt2x00_desc_write(entry_priv->desc, 1, word);
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}
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}
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static int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev)
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{
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struct queue_entry_priv_mmio *entry_priv;
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/*
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* Initialize registers.
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*/
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entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
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rt2x00dev->tx[0].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
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entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
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rt2x00dev->tx[1].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
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entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
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rt2x00dev->tx[2].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
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entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
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rt2x00dev->tx[3].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
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entry_priv = rt2x00dev->rx->entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
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rt2x00dev->rx[0].limit);
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rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
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rt2x00dev->rx[0].limit - 1);
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rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
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rt2800_disable_wpdma(rt2x00dev);
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rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
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return 0;
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}
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/*
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* Device state switch handlers.
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*/
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static int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev)
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{
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u32 reg;
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/*
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* Reset DMA indexes
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*/
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rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
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rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
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if (rt2x00_is_pcie(rt2x00dev) &&
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(rt2x00_rt(rt2x00dev, RT3090) ||
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rt2x00_rt(rt2x00dev, RT3390) ||
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rt2x00_rt(rt2x00dev, RT3572) ||
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rt2x00_rt(rt2x00dev, RT3593) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392) ||
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rt2x00_rt(rt2x00dev, RT5592))) {
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rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, ®);
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rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
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rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
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rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
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}
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rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
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reg = 0;
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rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
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rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
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rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
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rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
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return 0;
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}
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static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
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{
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int retval;
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|
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/* Wait for DMA, ignore error until we initialize queues. */
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rt2800_wait_wpdma_ready(rt2x00dev);
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|
|
if (unlikely(rt2800mmio_init_queues(rt2x00dev)))
|
|
return -EIO;
|
|
|
|
retval = rt2800_enable_radio(rt2x00dev);
|
|
if (retval)
|
|
return retval;
|
|
|
|
/* After resume MCU_BOOT_SIGNAL will trash these. */
|
|
rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
|
|
rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
|
|
|
|
rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
|
|
rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
|
|
|
|
rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
|
|
rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
if (rt2x00_is_soc(rt2x00dev)) {
|
|
rt2800_disable_radio(rt2x00dev);
|
|
rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
|
|
rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
|
|
}
|
|
}
|
|
|
|
static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
|
|
enum dev_state state)
|
|
{
|
|
if (state == STATE_AWAKE) {
|
|
rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
|
|
0, 0x02);
|
|
rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
|
|
} else if (state == STATE_SLEEP) {
|
|
rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
|
|
0xffffffff);
|
|
rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
|
|
0xffffffff);
|
|
rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
|
|
0xff, 0x01);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
|
|
enum dev_state state)
|
|
{
|
|
int retval = 0;
|
|
|
|
switch (state) {
|
|
case STATE_RADIO_ON:
|
|
retval = rt2800pci_enable_radio(rt2x00dev);
|
|
break;
|
|
case STATE_RADIO_OFF:
|
|
/*
|
|
* After the radio has been disabled, the device should
|
|
* be put to sleep for powersaving.
|
|
*/
|
|
rt2800pci_disable_radio(rt2x00dev);
|
|
rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
|
|
break;
|
|
case STATE_RADIO_IRQ_ON:
|
|
case STATE_RADIO_IRQ_OFF:
|
|
rt2800mmio_toggle_irq(rt2x00dev, state);
|
|
break;
|
|
case STATE_DEEP_SLEEP:
|
|
case STATE_SLEEP:
|
|
case STATE_STANDBY:
|
|
case STATE_AWAKE:
|
|
retval = rt2800pci_set_state(rt2x00dev, state);
|
|
break;
|
|
default:
|
|
retval = -ENOTSUPP;
|
|
break;
|
|
}
|
|
|
|
if (unlikely(retval))
|
|
rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
|
|
state, retval);
|
|
|
|
return retval;
|
|
}
|
|
|
|
/*
|
|
* Device probe functions.
|
|
*/
|
|
static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
int retval;
|
|
|
|
if (rt2x00_is_soc(rt2x00dev))
|
|
retval = rt2800pci_read_eeprom_soc(rt2x00dev);
|
|
else if (rt2800pci_efuse_detect(rt2x00dev))
|
|
retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
|
|
else
|
|
retval = rt2800pci_read_eeprom_pci(rt2x00dev);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static const struct ieee80211_ops rt2800pci_mac80211_ops = {
|
|
.tx = rt2x00mac_tx,
|
|
.start = rt2x00mac_start,
|
|
.stop = rt2x00mac_stop,
|
|
.add_interface = rt2x00mac_add_interface,
|
|
.remove_interface = rt2x00mac_remove_interface,
|
|
.config = rt2x00mac_config,
|
|
.configure_filter = rt2x00mac_configure_filter,
|
|
.set_key = rt2x00mac_set_key,
|
|
.sw_scan_start = rt2x00mac_sw_scan_start,
|
|
.sw_scan_complete = rt2x00mac_sw_scan_complete,
|
|
.get_stats = rt2x00mac_get_stats,
|
|
.get_tkip_seq = rt2800_get_tkip_seq,
|
|
.set_rts_threshold = rt2800_set_rts_threshold,
|
|
.sta_add = rt2x00mac_sta_add,
|
|
.sta_remove = rt2x00mac_sta_remove,
|
|
.bss_info_changed = rt2x00mac_bss_info_changed,
|
|
.conf_tx = rt2800_conf_tx,
|
|
.get_tsf = rt2800_get_tsf,
|
|
.rfkill_poll = rt2x00mac_rfkill_poll,
|
|
.ampdu_action = rt2800_ampdu_action,
|
|
.flush = rt2x00mac_flush,
|
|
.get_survey = rt2800_get_survey,
|
|
.get_ringparam = rt2x00mac_get_ringparam,
|
|
.tx_frames_pending = rt2x00mac_tx_frames_pending,
|
|
};
|
|
|
|
static const struct rt2800_ops rt2800pci_rt2800_ops = {
|
|
.register_read = rt2x00mmio_register_read,
|
|
.register_read_lock = rt2x00mmio_register_read, /* same for PCI */
|
|
.register_write = rt2x00mmio_register_write,
|
|
.register_write_lock = rt2x00mmio_register_write, /* same for PCI */
|
|
.register_multiread = rt2x00mmio_register_multiread,
|
|
.register_multiwrite = rt2x00mmio_register_multiwrite,
|
|
.regbusy_read = rt2x00mmio_regbusy_read,
|
|
.read_eeprom = rt2800pci_read_eeprom,
|
|
.hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
|
|
.drv_write_firmware = rt2800pci_write_firmware,
|
|
.drv_init_registers = rt2800mmio_init_registers,
|
|
.drv_get_txwi = rt2800mmio_get_txwi,
|
|
};
|
|
|
|
static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
|
|
.irq_handler = rt2800mmio_interrupt,
|
|
.txstatus_tasklet = rt2800mmio_txstatus_tasklet,
|
|
.pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
|
|
.tbtt_tasklet = rt2800mmio_tbtt_tasklet,
|
|
.rxdone_tasklet = rt2800mmio_rxdone_tasklet,
|
|
.autowake_tasklet = rt2800mmio_autowake_tasklet,
|
|
.probe_hw = rt2800_probe_hw,
|
|
.get_firmware_name = rt2800pci_get_firmware_name,
|
|
.check_firmware = rt2800_check_firmware,
|
|
.load_firmware = rt2800_load_firmware,
|
|
.initialize = rt2x00mmio_initialize,
|
|
.uninitialize = rt2x00mmio_uninitialize,
|
|
.get_entry_state = rt2800mmio_get_entry_state,
|
|
.clear_entry = rt2800mmio_clear_entry,
|
|
.set_device_state = rt2800pci_set_device_state,
|
|
.rfkill_poll = rt2800_rfkill_poll,
|
|
.link_stats = rt2800_link_stats,
|
|
.reset_tuner = rt2800_reset_tuner,
|
|
.link_tuner = rt2800_link_tuner,
|
|
.gain_calibration = rt2800_gain_calibration,
|
|
.vco_calibration = rt2800_vco_calibration,
|
|
.start_queue = rt2800mmio_start_queue,
|
|
.kick_queue = rt2800mmio_kick_queue,
|
|
.stop_queue = rt2800mmio_stop_queue,
|
|
.flush_queue = rt2x00mmio_flush_queue,
|
|
.write_tx_desc = rt2800mmio_write_tx_desc,
|
|
.write_tx_data = rt2800_write_tx_data,
|
|
.write_beacon = rt2800_write_beacon,
|
|
.clear_beacon = rt2800_clear_beacon,
|
|
.fill_rxdone = rt2800mmio_fill_rxdone,
|
|
.config_shared_key = rt2800_config_shared_key,
|
|
.config_pairwise_key = rt2800_config_pairwise_key,
|
|
.config_filter = rt2800_config_filter,
|
|
.config_intf = rt2800_config_intf,
|
|
.config_erp = rt2800_config_erp,
|
|
.config_ant = rt2800_config_ant,
|
|
.config = rt2800_config,
|
|
.sta_add = rt2800_sta_add,
|
|
.sta_remove = rt2800_sta_remove,
|
|
};
|
|
|
|
static const struct rt2x00_ops rt2800pci_ops = {
|
|
.name = KBUILD_MODNAME,
|
|
.drv_data_size = sizeof(struct rt2800_drv_data),
|
|
.max_ap_intf = 8,
|
|
.eeprom_size = EEPROM_SIZE,
|
|
.rf_size = RF_SIZE,
|
|
.tx_queues = NUM_TX_QUEUES,
|
|
.queue_init = rt2800mmio_queue_init,
|
|
.lib = &rt2800pci_rt2x00_ops,
|
|
.drv = &rt2800pci_rt2800_ops,
|
|
.hw = &rt2800pci_mac80211_ops,
|
|
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
|
|
.debugfs = &rt2800_rt2x00debug,
|
|
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
|
|
};
|
|
|
|
/*
|
|
* RT2800pci module information.
|
|
*/
|
|
#ifdef CONFIG_PCI
|
|
static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
|
|
{ PCI_DEVICE(0x1814, 0x0601) },
|
|
{ PCI_DEVICE(0x1814, 0x0681) },
|
|
{ PCI_DEVICE(0x1814, 0x0701) },
|
|
{ PCI_DEVICE(0x1814, 0x0781) },
|
|
{ PCI_DEVICE(0x1814, 0x3090) },
|
|
{ PCI_DEVICE(0x1814, 0x3091) },
|
|
{ PCI_DEVICE(0x1814, 0x3092) },
|
|
{ PCI_DEVICE(0x1432, 0x7708) },
|
|
{ PCI_DEVICE(0x1432, 0x7727) },
|
|
{ PCI_DEVICE(0x1432, 0x7728) },
|
|
{ PCI_DEVICE(0x1432, 0x7738) },
|
|
{ PCI_DEVICE(0x1432, 0x7748) },
|
|
{ PCI_DEVICE(0x1432, 0x7758) },
|
|
{ PCI_DEVICE(0x1432, 0x7768) },
|
|
{ PCI_DEVICE(0x1462, 0x891a) },
|
|
{ PCI_DEVICE(0x1a3b, 0x1059) },
|
|
#ifdef CONFIG_RT2800PCI_RT3290
|
|
{ PCI_DEVICE(0x1814, 0x3290) },
|
|
#endif
|
|
#ifdef CONFIG_RT2800PCI_RT33XX
|
|
{ PCI_DEVICE(0x1814, 0x3390) },
|
|
#endif
|
|
#ifdef CONFIG_RT2800PCI_RT35XX
|
|
{ PCI_DEVICE(0x1432, 0x7711) },
|
|
{ PCI_DEVICE(0x1432, 0x7722) },
|
|
{ PCI_DEVICE(0x1814, 0x3060) },
|
|
{ PCI_DEVICE(0x1814, 0x3062) },
|
|
{ PCI_DEVICE(0x1814, 0x3562) },
|
|
{ PCI_DEVICE(0x1814, 0x3592) },
|
|
{ PCI_DEVICE(0x1814, 0x3593) },
|
|
{ PCI_DEVICE(0x1814, 0x359f) },
|
|
#endif
|
|
#ifdef CONFIG_RT2800PCI_RT53XX
|
|
{ PCI_DEVICE(0x1814, 0x5360) },
|
|
{ PCI_DEVICE(0x1814, 0x5362) },
|
|
{ PCI_DEVICE(0x1814, 0x5390) },
|
|
{ PCI_DEVICE(0x1814, 0x5392) },
|
|
{ PCI_DEVICE(0x1814, 0x539a) },
|
|
{ PCI_DEVICE(0x1814, 0x539b) },
|
|
{ PCI_DEVICE(0x1814, 0x539f) },
|
|
#endif
|
|
{ 0, }
|
|
};
|
|
#endif /* CONFIG_PCI */
|
|
|
|
MODULE_AUTHOR(DRV_PROJECT);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
|
|
MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
|
|
#ifdef CONFIG_PCI
|
|
MODULE_FIRMWARE(FIRMWARE_RT2860);
|
|
MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
|
|
#endif /* CONFIG_PCI */
|
|
MODULE_LICENSE("GPL");
|
|
|
|
#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
|
|
static int rt2800soc_probe(struct platform_device *pdev)
|
|
{
|
|
return rt2x00soc_probe(pdev, &rt2800pci_ops);
|
|
}
|
|
|
|
static struct platform_driver rt2800soc_driver = {
|
|
.driver = {
|
|
.name = "rt2800_wmac",
|
|
.owner = THIS_MODULE,
|
|
.mod_name = KBUILD_MODNAME,
|
|
},
|
|
.probe = rt2800soc_probe,
|
|
.remove = rt2x00soc_remove,
|
|
.suspend = rt2x00soc_suspend,
|
|
.resume = rt2x00soc_resume,
|
|
};
|
|
#endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
|
|
|
|
#ifdef CONFIG_PCI
|
|
static int rt2800pci_probe(struct pci_dev *pci_dev,
|
|
const struct pci_device_id *id)
|
|
{
|
|
return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
|
|
}
|
|
|
|
static struct pci_driver rt2800pci_driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.id_table = rt2800pci_device_table,
|
|
.probe = rt2800pci_probe,
|
|
.remove = rt2x00pci_remove,
|
|
.suspend = rt2x00pci_suspend,
|
|
.resume = rt2x00pci_resume,
|
|
};
|
|
#endif /* CONFIG_PCI */
|
|
|
|
static int __init rt2800pci_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
|
|
ret = platform_driver_register(&rt2800soc_driver);
|
|
if (ret)
|
|
return ret;
|
|
#endif
|
|
#ifdef CONFIG_PCI
|
|
ret = pci_register_driver(&rt2800pci_driver);
|
|
if (ret) {
|
|
#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
|
|
platform_driver_unregister(&rt2800soc_driver);
|
|
#endif
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit rt2800pci_exit(void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
pci_unregister_driver(&rt2800pci_driver);
|
|
#endif
|
|
#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
|
|
platform_driver_unregister(&rt2800soc_driver);
|
|
#endif
|
|
}
|
|
|
|
module_init(rt2800pci_init);
|
|
module_exit(rt2800pci_exit);
|