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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e070fb743d
On some m32r platforms, cascaded ICUs are used. This patch is required to simplify ei_handler and consolidate platform- dependent ICU check routines. platform ICU/INT1 ICU/INT0 ICU/INT2 -------------- -------- -------- -------- m32104ut o - - m32700ut o o o opsput o o o usrv o - - (others) - - - Signed-off-by: Hitoshi Yamamoto <hitoshiy@linux-m32r.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
161 lines
5.7 KiB
C
161 lines
5.7 KiB
C
#ifndef _ASM_M32R_M32R_H_
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#define _ASM_M32R_M32R_H_
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/*
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* Renesas M32R processor
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*
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* Copyright (C) 2003, 2004 Renesas Technology Corp.
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*/
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/* Chip type */
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#if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
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#include <asm/m32r_mp_fpga.h>
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#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
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|| defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
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|| defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
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#include <asm/m32102.h>
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#endif
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/* Platform type */
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#if defined(CONFIG_PLAT_M32700UT)
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#include <asm/m32700ut/m32700ut_pld.h>
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#include <asm/m32700ut/m32700ut_lan.h>
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#include <asm/m32700ut/m32700ut_lcd.h>
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/* for ei_handler:linux/arch/m32r/kernel/entry.S */
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#define M32R_INT1ICU_ISTS PLD_ICUISTS
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#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE
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#define M32R_INT0ICU_ISTS M32700UT_LAN_ICUISTS
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#define M32R_INT0ICU_IRQ_BASE M32700UT_LAN_PLD_IRQ_BASE
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#define M32R_INT2ICU_ISTS M32700UT_LCD_ICUISTS
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#define M32R_INT2ICU_IRQ_BASE M32700UT_LCD_PLD_IRQ_BASE
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#endif /* CONFIG_PLAT_M32700UT */
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#if defined(CONFIG_PLAT_OPSPUT)
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#include <asm/opsput/opsput_pld.h>
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#include <asm/opsput/opsput_lan.h>
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#include <asm/opsput/opsput_lcd.h>
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/* for ei_handler:linux/arch/m32r/kernel/entry.S */
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#define M32R_INT1ICU_ISTS PLD_ICUISTS
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#define M32R_INT1ICU_IRQ_BASE OPSPUT_PLD_IRQ_BASE
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#define M32R_INT0ICU_ISTS OPSPUT_LAN_ICUISTS
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#define M32R_INT0ICU_IRQ_BASE OPSPUT_LAN_PLD_IRQ_BASE
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#define M32R_INT2ICU_ISTS OPSPUT_LCD_ICUISTS
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#define M32R_INT2ICU_IRQ_BASE OPSPUT_LCD_PLD_IRQ_BASE
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#endif /* CONFIG_PLAT_OPSPUT */
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#if defined(CONFIG_PLAT_MAPPI2)
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#include <asm/mappi2/mappi2_pld.h>
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#endif /* CONFIG_PLAT_MAPPI2 */
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#if defined(CONFIG_PLAT_MAPPI3)
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#include <asm/mappi3/mappi3_pld.h>
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#endif /* CONFIG_PLAT_MAPPI3 */
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#if defined(CONFIG_PLAT_USRV)
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#include <asm/m32700ut/m32700ut_pld.h>
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/* for ei_handler:linux/arch/m32r/kernel/entry.S */
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#define M32R_INT1ICU_ISTS PLD_ICUISTS
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#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE
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#endif
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#if defined(CONFIG_PLAT_M32104UT)
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#include <asm/m32104ut/m32104ut_pld.h>
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/* for ei_handler:linux/arch/m32r/kernel/entry.S */
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#define M32R_INT1ICU_ISTS PLD_ICUISTS
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#define M32R_INT1ICU_IRQ_BASE M32104UT_PLD_IRQ_BASE
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#endif /* CONFIG_PLAT_M32104 */
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/*
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* M32R Register
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*/
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/*
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* MMU Register
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*/
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#define MMU_REG_BASE (0xffff0000)
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#define ITLB_BASE (0xfe000000)
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#define DTLB_BASE (0xfe000800)
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#define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES
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#define MATM MMU_REG_BASE /* MMU Address Translation Mode
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Register */
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#define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
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#define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
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#define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
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#define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
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Address Register */
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#define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
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Number Register */
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#define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
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#define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
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Register */
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#define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
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#define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
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Instruciton */
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#define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
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#define MATM_offset (MATM - MMU_REG_BASE)
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#define MPSZ_offset (MPSZ - MMU_REG_BASE)
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#define MASID_offset (MASID - MMU_REG_BASE)
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#define MESTS_offset (MESTS - MMU_REG_BASE)
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#define MDEVA_offset (MDEVA - MMU_REG_BASE)
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#define MDEVP_offset (MDEVP - MMU_REG_BASE)
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#define MPTB_offset (MPTB - MMU_REG_BASE)
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#define MSVA_offset (MSVA - MMU_REG_BASE)
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#define MTOP_offset (MTOP - MMU_REG_BASE)
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#define MIDXI_offset (MIDXI - MMU_REG_BASE)
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#define MIDXD_offset (MIDXD - MMU_REG_BASE)
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#define MESTS_IT (1 << 0) /* Instruction TLB miss */
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#define MESTS_IA (1 << 1) /* Instruction Access Exception */
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#define MESTS_DT (1 << 4) /* Operand TLB miss */
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#define MESTS_DA (1 << 5) /* Operand Access Exception */
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#define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */
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/*
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* PSW (Processor Status Word)
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*/
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/* PSW bit */
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#define M32R_PSW_BIT_SM (7) /* Stack Mode */
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#define M32R_PSW_BIT_IE (6) /* Interrupt Enable */
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#define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */
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#define M32R_PSW_BIT_C (0) /* Condition */
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#define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */
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#define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */
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#define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */
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#define M32R_PSW_BIT_BC (0+8) /* Backup Condition */
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/* PSW bit map */
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#define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */
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#define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */
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#define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */
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#define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */
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#define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */
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#define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */
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#define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */
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#define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */
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/*
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* Direct address to SFR
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*/
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#include <asm/page.h>
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#ifdef CONFIG_MMU
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#define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000)
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#else
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#define NONCACHE_OFFSET __PAGE_OFFSET
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#endif /* CONFIG_MMU */
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#define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
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#define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
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#define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
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#define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
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#define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
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#define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
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#endif /* _ASM_M32R_M32R_H_ */
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