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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5712846808
1. We were calling clear_flush_young_notify in unmap_one, but we are within an mmu notifier invalidate range scope. The spte exists no more (due to range_start) and the accessed bit info has already been propagated (due to kvm_pfn_set_accessed). Simply call clear_flush_young. 2. We clear_flush_young on a primary MMU PMD, but this may be mapped as a collection of PTEs by the secondary MMU (e.g. during log-dirty). This required expanding the interface of the clear_flush_young mmu notifier, so a lot of code has been trivially touched. 3. In the absence of shadow_accessed_mask (e.g. EPT A bit), we emulate the access bit by blowing the spte. This requires proper synchronizing with MMU notifier consumers, like every other removal of spte's does. Signed-off-by: Andres Lagar-Cavilla <andreslc@google.com> Acked-by: Rik van Riel <riel@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
1008 lines
22 KiB
C
1008 lines
22 KiB
C
/*
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* Copyright (C) 2010-2012 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/mmu_notifier.h>
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#include <linux/amd-iommu.h>
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#include <linux/mm_types.h>
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#include <linux/profile.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/iommu.h>
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#include <linux/wait.h>
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#include <linux/pci.h>
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#include <linux/gfp.h>
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#include "amd_iommu_types.h"
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#include "amd_iommu_proto.h"
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>");
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#define MAX_DEVICES 0x10000
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#define PRI_QUEUE_SIZE 512
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struct pri_queue {
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atomic_t inflight;
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bool finish;
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int status;
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};
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struct pasid_state {
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struct list_head list; /* For global state-list */
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atomic_t count; /* Reference count */
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unsigned mmu_notifier_count; /* Counting nested mmu_notifier
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calls */
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struct mm_struct *mm; /* mm_struct for the faults */
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struct mmu_notifier mn; /* mmu_notifier handle */
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struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */
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struct device_state *device_state; /* Link to our device_state */
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int pasid; /* PASID index */
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bool invalid; /* Used during setup and
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teardown of the pasid */
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spinlock_t lock; /* Protect pri_queues and
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mmu_notifer_count */
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wait_queue_head_t wq; /* To wait for count == 0 */
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};
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struct device_state {
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struct list_head list;
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u16 devid;
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atomic_t count;
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struct pci_dev *pdev;
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struct pasid_state **states;
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struct iommu_domain *domain;
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int pasid_levels;
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int max_pasids;
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amd_iommu_invalid_ppr_cb inv_ppr_cb;
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amd_iommu_invalidate_ctx inv_ctx_cb;
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spinlock_t lock;
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wait_queue_head_t wq;
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};
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struct fault {
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struct work_struct work;
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struct device_state *dev_state;
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struct pasid_state *state;
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struct mm_struct *mm;
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u64 address;
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u16 devid;
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u16 pasid;
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u16 tag;
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u16 finish;
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u16 flags;
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};
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static LIST_HEAD(state_list);
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static spinlock_t state_lock;
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static struct workqueue_struct *iommu_wq;
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/*
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* Empty page table - Used between
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* mmu_notifier_invalidate_range_start and
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* mmu_notifier_invalidate_range_end
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*/
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static u64 *empty_page_table;
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static void free_pasid_states(struct device_state *dev_state);
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static u16 device_id(struct pci_dev *pdev)
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{
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u16 devid;
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devid = pdev->bus->number;
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devid = (devid << 8) | pdev->devfn;
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return devid;
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}
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static struct device_state *__get_device_state(u16 devid)
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{
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struct device_state *dev_state;
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list_for_each_entry(dev_state, &state_list, list) {
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if (dev_state->devid == devid)
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return dev_state;
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}
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return NULL;
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}
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static struct device_state *get_device_state(u16 devid)
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{
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struct device_state *dev_state;
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unsigned long flags;
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spin_lock_irqsave(&state_lock, flags);
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dev_state = __get_device_state(devid);
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if (dev_state != NULL)
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atomic_inc(&dev_state->count);
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spin_unlock_irqrestore(&state_lock, flags);
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return dev_state;
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}
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static void free_device_state(struct device_state *dev_state)
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{
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/*
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* First detach device from domain - No more PRI requests will arrive
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* from that device after it is unbound from the IOMMUv2 domain.
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*/
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iommu_detach_device(dev_state->domain, &dev_state->pdev->dev);
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/* Everything is down now, free the IOMMUv2 domain */
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iommu_domain_free(dev_state->domain);
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/* Finally get rid of the device-state */
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kfree(dev_state);
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}
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static void put_device_state(struct device_state *dev_state)
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{
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if (atomic_dec_and_test(&dev_state->count))
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wake_up(&dev_state->wq);
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}
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static void put_device_state_wait(struct device_state *dev_state)
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{
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DEFINE_WAIT(wait);
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prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE);
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if (!atomic_dec_and_test(&dev_state->count))
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schedule();
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finish_wait(&dev_state->wq, &wait);
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free_device_state(dev_state);
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}
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/* Must be called under dev_state->lock */
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static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state,
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int pasid, bool alloc)
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{
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struct pasid_state **root, **ptr;
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int level, index;
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level = dev_state->pasid_levels;
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root = dev_state->states;
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while (true) {
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index = (pasid >> (9 * level)) & 0x1ff;
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ptr = &root[index];
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if (level == 0)
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break;
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if (*ptr == NULL) {
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if (!alloc)
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return NULL;
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*ptr = (void *)get_zeroed_page(GFP_ATOMIC);
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if (*ptr == NULL)
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return NULL;
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}
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root = (struct pasid_state **)*ptr;
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level -= 1;
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}
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return ptr;
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}
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static int set_pasid_state(struct device_state *dev_state,
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struct pasid_state *pasid_state,
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int pasid)
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{
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struct pasid_state **ptr;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&dev_state->lock, flags);
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ptr = __get_pasid_state_ptr(dev_state, pasid, true);
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ret = -ENOMEM;
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if (ptr == NULL)
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goto out_unlock;
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ret = -ENOMEM;
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if (*ptr != NULL)
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goto out_unlock;
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*ptr = pasid_state;
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ret = 0;
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out_unlock:
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spin_unlock_irqrestore(&dev_state->lock, flags);
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return ret;
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}
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static void clear_pasid_state(struct device_state *dev_state, int pasid)
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{
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struct pasid_state **ptr;
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unsigned long flags;
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spin_lock_irqsave(&dev_state->lock, flags);
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ptr = __get_pasid_state_ptr(dev_state, pasid, true);
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if (ptr == NULL)
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goto out_unlock;
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*ptr = NULL;
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out_unlock:
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spin_unlock_irqrestore(&dev_state->lock, flags);
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}
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static struct pasid_state *get_pasid_state(struct device_state *dev_state,
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int pasid)
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{
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struct pasid_state **ptr, *ret = NULL;
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unsigned long flags;
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spin_lock_irqsave(&dev_state->lock, flags);
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ptr = __get_pasid_state_ptr(dev_state, pasid, false);
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if (ptr == NULL)
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goto out_unlock;
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ret = *ptr;
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if (ret)
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atomic_inc(&ret->count);
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out_unlock:
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spin_unlock_irqrestore(&dev_state->lock, flags);
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return ret;
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}
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static void free_pasid_state(struct pasid_state *pasid_state)
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{
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kfree(pasid_state);
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}
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static void put_pasid_state(struct pasid_state *pasid_state)
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{
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if (atomic_dec_and_test(&pasid_state->count)) {
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put_device_state(pasid_state->device_state);
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wake_up(&pasid_state->wq);
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}
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}
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static void put_pasid_state_wait(struct pasid_state *pasid_state)
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{
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DEFINE_WAIT(wait);
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prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE);
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if (atomic_dec_and_test(&pasid_state->count))
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put_device_state(pasid_state->device_state);
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else
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schedule();
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finish_wait(&pasid_state->wq, &wait);
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free_pasid_state(pasid_state);
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}
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static void unbind_pasid(struct pasid_state *pasid_state)
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{
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struct iommu_domain *domain;
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domain = pasid_state->device_state->domain;
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/*
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* Mark pasid_state as invalid, no more faults will we added to the
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* work queue after this is visible everywhere.
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*/
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pasid_state->invalid = true;
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/* Make sure this is visible */
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smp_wmb();
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/* After this the device/pasid can't access the mm anymore */
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amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid);
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/* Make sure no more pending faults are in the queue */
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flush_workqueue(iommu_wq);
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}
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static void free_pasid_states_level1(struct pasid_state **tbl)
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{
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int i;
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for (i = 0; i < 512; ++i) {
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if (tbl[i] == NULL)
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continue;
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free_page((unsigned long)tbl[i]);
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}
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}
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static void free_pasid_states_level2(struct pasid_state **tbl)
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{
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struct pasid_state **ptr;
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int i;
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for (i = 0; i < 512; ++i) {
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if (tbl[i] == NULL)
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continue;
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ptr = (struct pasid_state **)tbl[i];
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free_pasid_states_level1(ptr);
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}
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}
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static void free_pasid_states(struct device_state *dev_state)
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{
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struct pasid_state *pasid_state;
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int i;
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for (i = 0; i < dev_state->max_pasids; ++i) {
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pasid_state = get_pasid_state(dev_state, i);
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if (pasid_state == NULL)
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continue;
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put_pasid_state(pasid_state);
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/*
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* This will call the mn_release function and
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* unbind the PASID
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*/
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mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
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put_pasid_state_wait(pasid_state); /* Reference taken in
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amd_iommu_bind_pasid */
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/* Drop reference taken in amd_iommu_bind_pasid */
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put_device_state(dev_state);
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}
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if (dev_state->pasid_levels == 2)
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free_pasid_states_level2(dev_state->states);
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else if (dev_state->pasid_levels == 1)
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free_pasid_states_level1(dev_state->states);
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else if (dev_state->pasid_levels != 0)
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BUG();
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free_page((unsigned long)dev_state->states);
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}
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static struct pasid_state *mn_to_state(struct mmu_notifier *mn)
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{
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return container_of(mn, struct pasid_state, mn);
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}
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static void __mn_flush_page(struct mmu_notifier *mn,
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unsigned long address)
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{
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struct pasid_state *pasid_state;
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struct device_state *dev_state;
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pasid_state = mn_to_state(mn);
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dev_state = pasid_state->device_state;
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amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address);
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}
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static int mn_clear_flush_young(struct mmu_notifier *mn,
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struct mm_struct *mm,
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unsigned long start,
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unsigned long end)
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{
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for (; start < end; start += PAGE_SIZE)
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__mn_flush_page(mn, start);
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return 0;
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}
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static void mn_invalidate_page(struct mmu_notifier *mn,
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struct mm_struct *mm,
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unsigned long address)
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{
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__mn_flush_page(mn, address);
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}
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static void mn_invalidate_range_start(struct mmu_notifier *mn,
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struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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struct pasid_state *pasid_state;
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struct device_state *dev_state;
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unsigned long flags;
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pasid_state = mn_to_state(mn);
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dev_state = pasid_state->device_state;
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spin_lock_irqsave(&pasid_state->lock, flags);
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if (pasid_state->mmu_notifier_count == 0) {
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amd_iommu_domain_set_gcr3(dev_state->domain,
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pasid_state->pasid,
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__pa(empty_page_table));
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}
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pasid_state->mmu_notifier_count += 1;
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spin_unlock_irqrestore(&pasid_state->lock, flags);
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}
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static void mn_invalidate_range_end(struct mmu_notifier *mn,
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struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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struct pasid_state *pasid_state;
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struct device_state *dev_state;
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unsigned long flags;
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pasid_state = mn_to_state(mn);
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dev_state = pasid_state->device_state;
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spin_lock_irqsave(&pasid_state->lock, flags);
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pasid_state->mmu_notifier_count -= 1;
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if (pasid_state->mmu_notifier_count == 0) {
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amd_iommu_domain_set_gcr3(dev_state->domain,
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pasid_state->pasid,
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__pa(pasid_state->mm->pgd));
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}
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spin_unlock_irqrestore(&pasid_state->lock, flags);
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}
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static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm)
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{
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struct pasid_state *pasid_state;
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struct device_state *dev_state;
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bool run_inv_ctx_cb;
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might_sleep();
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pasid_state = mn_to_state(mn);
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dev_state = pasid_state->device_state;
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run_inv_ctx_cb = !pasid_state->invalid;
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if (run_inv_ctx_cb && pasid_state->device_state->inv_ctx_cb)
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dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid);
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unbind_pasid(pasid_state);
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}
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static struct mmu_notifier_ops iommu_mn = {
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.release = mn_release,
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.clear_flush_young = mn_clear_flush_young,
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.invalidate_page = mn_invalidate_page,
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.invalidate_range_start = mn_invalidate_range_start,
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.invalidate_range_end = mn_invalidate_range_end,
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};
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static void set_pri_tag_status(struct pasid_state *pasid_state,
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u16 tag, int status)
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{
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unsigned long flags;
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spin_lock_irqsave(&pasid_state->lock, flags);
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pasid_state->pri[tag].status = status;
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spin_unlock_irqrestore(&pasid_state->lock, flags);
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}
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static void finish_pri_tag(struct device_state *dev_state,
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struct pasid_state *pasid_state,
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u16 tag)
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{
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unsigned long flags;
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spin_lock_irqsave(&pasid_state->lock, flags);
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if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) &&
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pasid_state->pri[tag].finish) {
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amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid,
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pasid_state->pri[tag].status, tag);
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pasid_state->pri[tag].finish = false;
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pasid_state->pri[tag].status = PPR_SUCCESS;
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}
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spin_unlock_irqrestore(&pasid_state->lock, flags);
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}
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static void do_fault(struct work_struct *work)
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{
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struct fault *fault = container_of(work, struct fault, work);
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int npages, write;
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struct page *page;
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write = !!(fault->flags & PPR_FAULT_WRITE);
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down_read(&fault->state->mm->mmap_sem);
|
|
npages = get_user_pages(NULL, fault->state->mm,
|
|
fault->address, 1, write, 0, &page, NULL);
|
|
up_read(&fault->state->mm->mmap_sem);
|
|
|
|
if (npages == 1) {
|
|
put_page(page);
|
|
} else if (fault->dev_state->inv_ppr_cb) {
|
|
int status;
|
|
|
|
status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev,
|
|
fault->pasid,
|
|
fault->address,
|
|
fault->flags);
|
|
switch (status) {
|
|
case AMD_IOMMU_INV_PRI_RSP_SUCCESS:
|
|
set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS);
|
|
break;
|
|
case AMD_IOMMU_INV_PRI_RSP_INVALID:
|
|
set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
|
|
break;
|
|
case AMD_IOMMU_INV_PRI_RSP_FAIL:
|
|
set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE);
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
} else {
|
|
set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
|
|
}
|
|
|
|
finish_pri_tag(fault->dev_state, fault->state, fault->tag);
|
|
|
|
put_pasid_state(fault->state);
|
|
|
|
kfree(fault);
|
|
}
|
|
|
|
static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
|
|
{
|
|
struct amd_iommu_fault *iommu_fault;
|
|
struct pasid_state *pasid_state;
|
|
struct device_state *dev_state;
|
|
unsigned long flags;
|
|
struct fault *fault;
|
|
bool finish;
|
|
u16 tag;
|
|
int ret;
|
|
|
|
iommu_fault = data;
|
|
tag = iommu_fault->tag & 0x1ff;
|
|
finish = (iommu_fault->tag >> 9) & 1;
|
|
|
|
ret = NOTIFY_DONE;
|
|
dev_state = get_device_state(iommu_fault->device_id);
|
|
if (dev_state == NULL)
|
|
goto out;
|
|
|
|
pasid_state = get_pasid_state(dev_state, iommu_fault->pasid);
|
|
if (pasid_state == NULL || pasid_state->invalid) {
|
|
/* We know the device but not the PASID -> send INVALID */
|
|
amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid,
|
|
PPR_INVALID, tag);
|
|
goto out_drop_state;
|
|
}
|
|
|
|
spin_lock_irqsave(&pasid_state->lock, flags);
|
|
atomic_inc(&pasid_state->pri[tag].inflight);
|
|
if (finish)
|
|
pasid_state->pri[tag].finish = true;
|
|
spin_unlock_irqrestore(&pasid_state->lock, flags);
|
|
|
|
fault = kzalloc(sizeof(*fault), GFP_ATOMIC);
|
|
if (fault == NULL) {
|
|
/* We are OOM - send success and let the device re-fault */
|
|
finish_pri_tag(dev_state, pasid_state, tag);
|
|
goto out_drop_state;
|
|
}
|
|
|
|
fault->dev_state = dev_state;
|
|
fault->address = iommu_fault->address;
|
|
fault->state = pasid_state;
|
|
fault->tag = tag;
|
|
fault->finish = finish;
|
|
fault->pasid = iommu_fault->pasid;
|
|
fault->flags = iommu_fault->flags;
|
|
INIT_WORK(&fault->work, do_fault);
|
|
|
|
queue_work(iommu_wq, &fault->work);
|
|
|
|
ret = NOTIFY_OK;
|
|
|
|
out_drop_state:
|
|
|
|
if (ret != NOTIFY_OK && pasid_state)
|
|
put_pasid_state(pasid_state);
|
|
|
|
put_device_state(dev_state);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static struct notifier_block ppr_nb = {
|
|
.notifier_call = ppr_notifier,
|
|
};
|
|
|
|
int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
|
|
struct task_struct *task)
|
|
{
|
|
struct pasid_state *pasid_state;
|
|
struct device_state *dev_state;
|
|
struct mm_struct *mm;
|
|
u16 devid;
|
|
int ret;
|
|
|
|
might_sleep();
|
|
|
|
if (!amd_iommu_v2_supported())
|
|
return -ENODEV;
|
|
|
|
devid = device_id(pdev);
|
|
dev_state = get_device_state(devid);
|
|
|
|
if (dev_state == NULL)
|
|
return -EINVAL;
|
|
|
|
ret = -EINVAL;
|
|
if (pasid < 0 || pasid >= dev_state->max_pasids)
|
|
goto out;
|
|
|
|
ret = -ENOMEM;
|
|
pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL);
|
|
if (pasid_state == NULL)
|
|
goto out;
|
|
|
|
|
|
atomic_set(&pasid_state->count, 1);
|
|
init_waitqueue_head(&pasid_state->wq);
|
|
spin_lock_init(&pasid_state->lock);
|
|
|
|
mm = get_task_mm(task);
|
|
pasid_state->mm = mm;
|
|
pasid_state->device_state = dev_state;
|
|
pasid_state->pasid = pasid;
|
|
pasid_state->invalid = true; /* Mark as valid only if we are
|
|
done with setting up the pasid */
|
|
pasid_state->mn.ops = &iommu_mn;
|
|
|
|
if (pasid_state->mm == NULL)
|
|
goto out_free;
|
|
|
|
mmu_notifier_register(&pasid_state->mn, mm);
|
|
|
|
ret = set_pasid_state(dev_state, pasid_state, pasid);
|
|
if (ret)
|
|
goto out_unregister;
|
|
|
|
ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid,
|
|
__pa(pasid_state->mm->pgd));
|
|
if (ret)
|
|
goto out_clear_state;
|
|
|
|
/* Now we are ready to handle faults */
|
|
pasid_state->invalid = false;
|
|
|
|
/*
|
|
* Drop the reference to the mm_struct here. We rely on the
|
|
* mmu_notifier release call-back to inform us when the mm
|
|
* is going away.
|
|
*/
|
|
mmput(mm);
|
|
|
|
return 0;
|
|
|
|
out_clear_state:
|
|
clear_pasid_state(dev_state, pasid);
|
|
|
|
out_unregister:
|
|
mmu_notifier_unregister(&pasid_state->mn, mm);
|
|
|
|
out_free:
|
|
mmput(mm);
|
|
free_pasid_state(pasid_state);
|
|
|
|
out:
|
|
put_device_state(dev_state);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(amd_iommu_bind_pasid);
|
|
|
|
void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid)
|
|
{
|
|
struct pasid_state *pasid_state;
|
|
struct device_state *dev_state;
|
|
u16 devid;
|
|
|
|
might_sleep();
|
|
|
|
if (!amd_iommu_v2_supported())
|
|
return;
|
|
|
|
devid = device_id(pdev);
|
|
dev_state = get_device_state(devid);
|
|
if (dev_state == NULL)
|
|
return;
|
|
|
|
if (pasid < 0 || pasid >= dev_state->max_pasids)
|
|
goto out;
|
|
|
|
pasid_state = get_pasid_state(dev_state, pasid);
|
|
if (pasid_state == NULL)
|
|
goto out;
|
|
/*
|
|
* Drop reference taken here. We are safe because we still hold
|
|
* the reference taken in the amd_iommu_bind_pasid function.
|
|
*/
|
|
put_pasid_state(pasid_state);
|
|
|
|
/* Clear the pasid state so that the pasid can be re-used */
|
|
clear_pasid_state(dev_state, pasid_state->pasid);
|
|
|
|
/*
|
|
* Call mmu_notifier_unregister to drop our reference
|
|
* to pasid_state->mm
|
|
*/
|
|
mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
|
|
|
|
put_pasid_state_wait(pasid_state); /* Reference taken in
|
|
amd_iommu_bind_pasid */
|
|
out:
|
|
/* Drop reference taken in this function */
|
|
put_device_state(dev_state);
|
|
|
|
/* Drop reference taken in amd_iommu_bind_pasid */
|
|
put_device_state(dev_state);
|
|
}
|
|
EXPORT_SYMBOL(amd_iommu_unbind_pasid);
|
|
|
|
int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
|
|
{
|
|
struct device_state *dev_state;
|
|
unsigned long flags;
|
|
int ret, tmp;
|
|
u16 devid;
|
|
|
|
might_sleep();
|
|
|
|
if (!amd_iommu_v2_supported())
|
|
return -ENODEV;
|
|
|
|
if (pasids <= 0 || pasids > (PASID_MASK + 1))
|
|
return -EINVAL;
|
|
|
|
devid = device_id(pdev);
|
|
|
|
dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL);
|
|
if (dev_state == NULL)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&dev_state->lock);
|
|
init_waitqueue_head(&dev_state->wq);
|
|
dev_state->pdev = pdev;
|
|
dev_state->devid = devid;
|
|
|
|
tmp = pasids;
|
|
for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9)
|
|
dev_state->pasid_levels += 1;
|
|
|
|
atomic_set(&dev_state->count, 1);
|
|
dev_state->max_pasids = pasids;
|
|
|
|
ret = -ENOMEM;
|
|
dev_state->states = (void *)get_zeroed_page(GFP_KERNEL);
|
|
if (dev_state->states == NULL)
|
|
goto out_free_dev_state;
|
|
|
|
dev_state->domain = iommu_domain_alloc(&pci_bus_type);
|
|
if (dev_state->domain == NULL)
|
|
goto out_free_states;
|
|
|
|
amd_iommu_domain_direct_map(dev_state->domain);
|
|
|
|
ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
|
|
if (ret)
|
|
goto out_free_domain;
|
|
|
|
ret = iommu_attach_device(dev_state->domain, &pdev->dev);
|
|
if (ret != 0)
|
|
goto out_free_domain;
|
|
|
|
spin_lock_irqsave(&state_lock, flags);
|
|
|
|
if (__get_device_state(devid) != NULL) {
|
|
spin_unlock_irqrestore(&state_lock, flags);
|
|
ret = -EBUSY;
|
|
goto out_free_domain;
|
|
}
|
|
|
|
list_add_tail(&dev_state->list, &state_list);
|
|
|
|
spin_unlock_irqrestore(&state_lock, flags);
|
|
|
|
return 0;
|
|
|
|
out_free_domain:
|
|
iommu_domain_free(dev_state->domain);
|
|
|
|
out_free_states:
|
|
free_page((unsigned long)dev_state->states);
|
|
|
|
out_free_dev_state:
|
|
kfree(dev_state);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(amd_iommu_init_device);
|
|
|
|
void amd_iommu_free_device(struct pci_dev *pdev)
|
|
{
|
|
struct device_state *dev_state;
|
|
unsigned long flags;
|
|
u16 devid;
|
|
|
|
if (!amd_iommu_v2_supported())
|
|
return;
|
|
|
|
devid = device_id(pdev);
|
|
|
|
spin_lock_irqsave(&state_lock, flags);
|
|
|
|
dev_state = __get_device_state(devid);
|
|
if (dev_state == NULL) {
|
|
spin_unlock_irqrestore(&state_lock, flags);
|
|
return;
|
|
}
|
|
|
|
list_del(&dev_state->list);
|
|
|
|
spin_unlock_irqrestore(&state_lock, flags);
|
|
|
|
/* Get rid of any remaining pasid states */
|
|
free_pasid_states(dev_state);
|
|
|
|
put_device_state_wait(dev_state);
|
|
}
|
|
EXPORT_SYMBOL(amd_iommu_free_device);
|
|
|
|
int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
|
|
amd_iommu_invalid_ppr_cb cb)
|
|
{
|
|
struct device_state *dev_state;
|
|
unsigned long flags;
|
|
u16 devid;
|
|
int ret;
|
|
|
|
if (!amd_iommu_v2_supported())
|
|
return -ENODEV;
|
|
|
|
devid = device_id(pdev);
|
|
|
|
spin_lock_irqsave(&state_lock, flags);
|
|
|
|
ret = -EINVAL;
|
|
dev_state = __get_device_state(devid);
|
|
if (dev_state == NULL)
|
|
goto out_unlock;
|
|
|
|
dev_state->inv_ppr_cb = cb;
|
|
|
|
ret = 0;
|
|
|
|
out_unlock:
|
|
spin_unlock_irqrestore(&state_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb);
|
|
|
|
int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
|
|
amd_iommu_invalidate_ctx cb)
|
|
{
|
|
struct device_state *dev_state;
|
|
unsigned long flags;
|
|
u16 devid;
|
|
int ret;
|
|
|
|
if (!amd_iommu_v2_supported())
|
|
return -ENODEV;
|
|
|
|
devid = device_id(pdev);
|
|
|
|
spin_lock_irqsave(&state_lock, flags);
|
|
|
|
ret = -EINVAL;
|
|
dev_state = __get_device_state(devid);
|
|
if (dev_state == NULL)
|
|
goto out_unlock;
|
|
|
|
dev_state->inv_ctx_cb = cb;
|
|
|
|
ret = 0;
|
|
|
|
out_unlock:
|
|
spin_unlock_irqrestore(&state_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb);
|
|
|
|
static int __init amd_iommu_v2_init(void)
|
|
{
|
|
int ret;
|
|
|
|
pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n");
|
|
|
|
if (!amd_iommu_v2_supported()) {
|
|
pr_info("AMD IOMMUv2 functionality not available on this system\n");
|
|
/*
|
|
* Load anyway to provide the symbols to other modules
|
|
* which may use AMD IOMMUv2 optionally.
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
spin_lock_init(&state_lock);
|
|
|
|
ret = -ENOMEM;
|
|
iommu_wq = create_workqueue("amd_iommu_v2");
|
|
if (iommu_wq == NULL)
|
|
goto out;
|
|
|
|
ret = -ENOMEM;
|
|
empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL);
|
|
if (empty_page_table == NULL)
|
|
goto out_destroy_wq;
|
|
|
|
amd_iommu_register_ppr_notifier(&ppr_nb);
|
|
|
|
return 0;
|
|
|
|
out_destroy_wq:
|
|
destroy_workqueue(iommu_wq);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static void __exit amd_iommu_v2_exit(void)
|
|
{
|
|
struct device_state *dev_state;
|
|
int i;
|
|
|
|
if (!amd_iommu_v2_supported())
|
|
return;
|
|
|
|
amd_iommu_unregister_ppr_notifier(&ppr_nb);
|
|
|
|
flush_workqueue(iommu_wq);
|
|
|
|
/*
|
|
* The loop below might call flush_workqueue(), so call
|
|
* destroy_workqueue() after it
|
|
*/
|
|
for (i = 0; i < MAX_DEVICES; ++i) {
|
|
dev_state = get_device_state(i);
|
|
|
|
if (dev_state == NULL)
|
|
continue;
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
put_device_state(dev_state);
|
|
amd_iommu_free_device(dev_state->pdev);
|
|
}
|
|
|
|
destroy_workqueue(iommu_wq);
|
|
|
|
free_page((unsigned long)empty_page_table);
|
|
}
|
|
|
|
module_init(amd_iommu_v2_init);
|
|
module_exit(amd_iommu_v2_exit);
|