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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1fe565517b
Implement all the event channel port ops for the FIFO-based ABI. If the hypervisor supports the FIFO-based ABI, enable it by initializing the control block for the boot VCPU and subsequent VCPUs as they are brought up and on resume. The event array is expanded as required when event ports are setup. The 'xen.fifo_events=0' command line option may be used to disable use of the FIFO-based ABI. Signed-off-by: David Vrabel <david.vrabel@citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
151 lines
3.2 KiB
C
151 lines
3.2 KiB
C
/*
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* Xen Event Channels (internal header)
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*
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* Copyright (C) 2013 Citrix Systems R&D Ltd.
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*
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* This source code is licensed under the GNU General Public License,
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* Version 2 or later. See the file COPYING for more details.
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*/
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#ifndef __EVENTS_INTERNAL_H__
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#define __EVENTS_INTERNAL_H__
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/* Interrupt types. */
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enum xen_irq_type {
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IRQT_UNBOUND = 0,
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IRQT_PIRQ,
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IRQT_VIRQ,
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IRQT_IPI,
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IRQT_EVTCHN
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};
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/*
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* Packed IRQ information:
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* type - enum xen_irq_type
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* event channel - irq->event channel mapping
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* cpu - cpu this event channel is bound to
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* index - type-specific information:
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* PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
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* guest, or GSI (real passthrough IRQ) of the device.
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* VIRQ - virq number
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* IPI - IPI vector
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* EVTCHN -
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*/
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struct irq_info {
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struct list_head list;
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int refcnt;
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enum xen_irq_type type; /* type */
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unsigned irq;
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unsigned int evtchn; /* event channel */
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unsigned short cpu; /* cpu bound */
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union {
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unsigned short virq;
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enum ipi_vector ipi;
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struct {
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unsigned short pirq;
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unsigned short gsi;
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unsigned char vector;
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unsigned char flags;
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uint16_t domid;
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} pirq;
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} u;
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};
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#define PIRQ_NEEDS_EOI (1 << 0)
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#define PIRQ_SHAREABLE (1 << 1)
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struct evtchn_ops {
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unsigned (*max_channels)(void);
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unsigned (*nr_channels)(void);
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int (*setup)(struct irq_info *info);
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void (*bind_to_cpu)(struct irq_info *info, unsigned cpu);
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void (*clear_pending)(unsigned port);
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void (*set_pending)(unsigned port);
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bool (*is_pending)(unsigned port);
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bool (*test_and_set_mask)(unsigned port);
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void (*mask)(unsigned port);
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void (*unmask)(unsigned port);
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void (*handle_events)(unsigned cpu);
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void (*resume)(void);
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};
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extern const struct evtchn_ops *evtchn_ops;
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extern int **evtchn_to_irq;
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int get_evtchn_to_irq(unsigned int evtchn);
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struct irq_info *info_for_irq(unsigned irq);
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unsigned cpu_from_irq(unsigned irq);
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unsigned cpu_from_evtchn(unsigned int evtchn);
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static inline unsigned xen_evtchn_max_channels(void)
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{
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return evtchn_ops->max_channels();
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}
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/*
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* Do any ABI specific setup for a bound event channel before it can
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* be unmasked and used.
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*/
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static inline int xen_evtchn_port_setup(struct irq_info *info)
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{
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if (evtchn_ops->setup)
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return evtchn_ops->setup(info);
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return 0;
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}
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static inline void xen_evtchn_port_bind_to_cpu(struct irq_info *info,
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unsigned cpu)
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{
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evtchn_ops->bind_to_cpu(info, cpu);
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}
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static inline void clear_evtchn(unsigned port)
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{
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evtchn_ops->clear_pending(port);
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}
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static inline void set_evtchn(unsigned port)
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{
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evtchn_ops->set_pending(port);
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}
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static inline bool test_evtchn(unsigned port)
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{
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return evtchn_ops->is_pending(port);
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}
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static inline bool test_and_set_mask(unsigned port)
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{
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return evtchn_ops->test_and_set_mask(port);
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}
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static inline void mask_evtchn(unsigned port)
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{
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return evtchn_ops->mask(port);
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}
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static inline void unmask_evtchn(unsigned port)
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{
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return evtchn_ops->unmask(port);
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}
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static inline void xen_evtchn_handle_events(unsigned cpu)
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{
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return evtchn_ops->handle_events(cpu);
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}
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static inline void xen_evtchn_resume(void)
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{
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if (evtchn_ops->resume)
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evtchn_ops->resume();
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}
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void xen_evtchn_2l_init(void);
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int xen_evtchn_fifo_init(void);
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#endif /* #ifndef __EVENTS_INTERNAL_H__ */
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