mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 22:40:55 +07:00
7e4992288e
Support ssp devices in PXA168. PXA168 could reuse the code of PXA SSP. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
150 lines
4.6 KiB
C
150 lines
4.6 KiB
C
/*
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* linux/arch/arm/mach-mmp/pxa168.c
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*
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* Code specific to PXA168
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/mach/time.h>
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#include <mach/addr-map.h>
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#include <mach/cputype.h>
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#include <mach/regs-apbc.h>
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#include <mach/regs-apmu.h>
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#include <mach/irqs.h>
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#include <mach/gpio.h>
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#include <mach/dma.h>
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#include <mach/devices.h>
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#include <mach/mfp.h>
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#include "common.h"
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#include "clock.h"
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#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
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static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata =
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{
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MFP_ADDR_X(GPIO0, GPIO36, 0x04c),
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MFP_ADDR_X(GPIO37, GPIO55, 0x000),
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MFP_ADDR_X(GPIO56, GPIO123, 0x0e0),
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MFP_ADDR_X(GPIO124, GPIO127, 0x0f4),
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MFP_ADDR_END,
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};
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#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
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static void __init pxa168_init_gpio(void)
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{
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int i;
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/* enable GPIO clock */
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__raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO);
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/* unmask GPIO edge detection for all 4 banks - APMASKx */
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for (i = 0; i < 4; i++)
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__raw_writel(0xffffffff, APMASK(i));
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pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL);
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}
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void __init pxa168_init_irq(void)
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{
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icu_init_irq();
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pxa168_init_gpio();
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}
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/* APB peripheral clocks */
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static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
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static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
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static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
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static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
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static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
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static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
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static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
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static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
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static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
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static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
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static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
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static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
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static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
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static APMU_CLK(nand, NAND, 0x01db, 208000000);
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/* device and clock bindings */
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static struct clk_lookup pxa168_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
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INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
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INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
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INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
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INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
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INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
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INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
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INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
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INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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};
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static int __init pxa168_init(void)
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{
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if (cpu_is_pxa168()) {
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mfp_init_base(MFPR_VIRT_BASE);
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mfp_init_addr(pxa168_mfp_addr_map);
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pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
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clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
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}
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return 0;
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}
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postcore_initcall(pxa168_init);
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/* system timer - clock enabled, 3.25MHz */
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#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
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static void __init pxa168_timer_init(void)
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{
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/* this is early, we have to initialize the CCU registers by
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* ourselves instead of using clk_* API. Clock rate is defined
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* by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
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*/
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__raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
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/* 3.25MHz, bus/functional clock enabled, release reset */
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__raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
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timer_init(IRQ_PXA168_TIMER1);
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}
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struct sys_timer pxa168_timer = {
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.init = pxa168_timer_init,
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};
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/* on-chip devices */
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PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
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PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
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PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
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PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
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PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
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PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10);
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PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10);
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PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10);
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PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
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PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53);
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PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
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PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
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PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
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PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
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