mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 16:46:49 +07:00
09180e5b4e
SiRFmarco is a dual-core cortex-a9 SMP SoC from CSR. this patch adds the .dtsi and a basic evb board .dts for it. Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com>
757 lines
16 KiB
Plaintext
757 lines
16 KiB
Plaintext
/*
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* DTS file for CSR SiRFmarco SoC
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "sirf,marco";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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axi {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x40000000 0x40000000 0xa0000000>;
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l2-cache-controller@c0030000 {
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compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
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reg = <0xc0030000 0x1000>;
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interrupts = <0 59 0>;
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arm,tag-latency = <1 1 1>;
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arm,data-latency = <1 1 1>;
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arm,filter-ranges = <0x40000000 0x80000000>;
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};
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gic: interrupt-controller@c0011000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0xc0011000 0x1000>,
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<0xc0010100 0x0100>;
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};
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rstc-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xc2000000 0xc2000000 0x1000000>;
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reset-controller@c2000000 {
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compatible = "sirf,marco-rstc";
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reg = <0xc2000000 0x10000>;
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};
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};
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sys-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xc3000000 0xc3000000 0x1000000>;
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clock-controller@c3000000 {
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compatible = "sirf,marco-clkc";
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reg = <0xc3000000 0x1000>;
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interrupts = <0 3 0>;
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};
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rsc-controller@c3010000 {
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compatible = "sirf,marco-rsc";
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reg = <0xc3010000 0x1000>;
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};
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};
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mem-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xc4000000 0xc4000000 0x1000000>;
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memory-controller@c4000000 {
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compatible = "sirf,marco-memc";
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reg = <0xc4000000 0x10000>;
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interrupts = <0 27 0>;
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};
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};
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disp-iobg0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xc5000000 0xc5000000 0x1000000>;
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display0@c5000000 {
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compatible = "sirf,marco-lcd";
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reg = <0xc5000000 0x10000>;
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interrupts = <0 30 0>;
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};
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vpp0@c5010000 {
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compatible = "sirf,marco-vpp";
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reg = <0xc5010000 0x10000>;
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interrupts = <0 31 0>;
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};
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};
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disp-iobg1 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xc6000000 0xc6000000 0x1000000>;
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display1@c6000000 {
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compatible = "sirf,marco-lcd";
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reg = <0xc6000000 0x10000>;
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interrupts = <0 62 0>;
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};
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vpp1@c6010000 {
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compatible = "sirf,marco-vpp";
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reg = <0xc6010000 0x10000>;
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interrupts = <0 63 0>;
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};
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};
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graphics-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xc8000000 0xc8000000 0x1000000>;
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graphics@c8000000 {
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compatible = "powervr,sgx540";
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reg = <0xc8000000 0x1000000>;
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interrupts = <0 6 0>;
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};
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};
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multimedia-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xc9000000 0xc9000000 0x1000000>;
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multimedia@a0000000 {
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compatible = "sirf,marco-video-codec";
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reg = <0xc9000000 0x1000000>;
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interrupts = <0 5 0>;
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};
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};
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dsp-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xca000000 0xca000000 0x2000000>;
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dspif@ca000000 {
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compatible = "sirf,marco-dspif";
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reg = <0xca000000 0x10000>;
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interrupts = <0 9 0>;
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};
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gps@ca010000 {
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compatible = "sirf,marco-gps";
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reg = <0xca010000 0x10000>;
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interrupts = <0 7 0>;
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};
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dsp@cb000000 {
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compatible = "sirf,marco-dsp";
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reg = <0xcb000000 0x1000000>;
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interrupts = <0 8 0>;
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};
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};
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peri-iobg {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xcc000000 0xcc000000 0x2000000>;
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timer@cc020000 {
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compatible = "sirf,marco-tick";
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reg = <0xcc020000 0x1000>;
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interrupts = <0 0 0>,
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<0 1 0>,
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<0 2 0>,
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<0 49 0>,
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<0 50 0>,
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<0 51 0>;
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};
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nand@cc030000 {
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compatible = "sirf,marco-nand";
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reg = <0xcc030000 0x10000>;
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interrupts = <0 41 0>;
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};
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audio@cc040000 {
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compatible = "sirf,marco-audio";
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reg = <0xcc040000 0x10000>;
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interrupts = <0 35 0>;
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};
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uart0: uart@cc050000 {
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cell-index = <0>;
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compatible = "sirf,marco-uart";
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reg = <0xcc050000 0x1000>;
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interrupts = <0 17 0>;
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fifosize = <128>;
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status = "disabled";
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};
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uart1: uart@cc060000 {
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cell-index = <1>;
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compatible = "sirf,marco-uart";
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reg = <0xcc060000 0x1000>;
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interrupts = <0 18 0>;
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fifosize = <32>;
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status = "disabled";
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};
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uart2: uart@cc070000 {
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cell-index = <2>;
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compatible = "sirf,marco-uart";
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reg = <0xcc070000 0x1000>;
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interrupts = <0 19 0>;
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fifosize = <128>;
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status = "disabled";
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};
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uart3: uart@cc190000 {
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cell-index = <3>;
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compatible = "sirf,marco-uart";
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reg = <0xcc190000 0x1000>;
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interrupts = <0 66 0>;
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fifosize = <128>;
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status = "disabled";
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};
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uart4: uart@cc1a0000 {
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cell-index = <4>;
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compatible = "sirf,marco-uart";
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reg = <0xcc1a0000 0x1000>;
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interrupts = <0 69 0>;
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fifosize = <128>;
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status = "disabled";
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};
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usp0: usp@cc080000 {
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cell-index = <0>;
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compatible = "sirf,marco-usp";
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reg = <0xcc080000 0x10000>;
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interrupts = <0 20 0>;
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status = "disabled";
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};
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usp1: usp@cc090000 {
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cell-index = <1>;
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compatible = "sirf,marco-usp";
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reg = <0xcc090000 0x10000>;
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interrupts = <0 21 0>;
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status = "disabled";
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};
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usp2: usp@cc0a0000 {
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cell-index = <2>;
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compatible = "sirf,marco-usp";
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reg = <0xcc0a0000 0x10000>;
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interrupts = <0 22 0>;
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status = "disabled";
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};
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dmac0: dma-controller@cc0b0000 {
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cell-index = <0>;
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compatible = "sirf,marco-dmac";
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reg = <0xcc0b0000 0x10000>;
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interrupts = <0 12 0>;
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};
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dmac1: dma-controller@cc160000 {
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cell-index = <1>;
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compatible = "sirf,marco-dmac";
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reg = <0xcc160000 0x10000>;
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interrupts = <0 13 0>;
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};
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vip@cc0c0000 {
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compatible = "sirf,marco-vip";
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reg = <0xcc0c0000 0x10000>;
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};
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spi0: spi@cc0d0000 {
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cell-index = <0>;
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compatible = "sirf,marco-spi";
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reg = <0xcc0d0000 0x10000>;
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interrupts = <0 15 0>;
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sirf,spi-num-chipselects = <1>;
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cs-gpios = <&gpio 0 0>;
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sirf,spi-dma-rx-channel = <25>;
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sirf,spi-dma-tx-channel = <20>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@cc170000 {
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cell-index = <1>;
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compatible = "sirf,marco-spi";
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reg = <0xcc170000 0x10000>;
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interrupts = <0 16 0>;
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sirf,spi-num-chipselects = <1>;
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cs-gpios = <&gpio 0 0>;
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sirf,spi-dma-rx-channel = <12>;
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sirf,spi-dma-tx-channel = <13>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c0: i2c@cc0e0000 {
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cell-index = <0>;
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compatible = "sirf,marco-i2c";
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reg = <0xcc0e0000 0x10000>;
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interrupts = <0 24 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@cc0f0000 {
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cell-index = <1>;
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compatible = "sirf,marco-i2c";
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reg = <0xcc0f0000 0x10000>;
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interrupts = <0 25 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tsc@cc110000 {
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compatible = "sirf,marco-tsc";
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reg = <0xcc110000 0x10000>;
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interrupts = <0 33 0>;
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};
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gpio: pinctrl@cc120000 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "sirf,marco-pinctrl";
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reg = <0xcc120000 0x10000>;
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interrupts = <0 43 0>,
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<0 44 0>,
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<0 45 0>,
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<0 46 0>,
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<0 47 0>;
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gpio-controller;
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interrupt-controller;
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lcd_16pins_a: lcd0_0 {
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lcd {
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sirf,pins = "lcd_16bitsgrp";
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sirf,function = "lcd_16bits";
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};
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};
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lcd_18pins_a: lcd0_1 {
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lcd {
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sirf,pins = "lcd_18bitsgrp";
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sirf,function = "lcd_18bits";
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};
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};
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lcd_24pins_a: lcd0_2 {
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lcd {
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sirf,pins = "lcd_24bitsgrp";
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sirf,function = "lcd_24bits";
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};
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};
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lcdrom_pins_a: lcdrom0_0 {
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lcd {
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sirf,pins = "lcdromgrp";
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sirf,function = "lcdrom";
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};
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};
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uart0_pins_a: uart0_0 {
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uart {
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sirf,pins = "uart0grp";
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sirf,function = "uart0";
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};
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};
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uart1_pins_a: uart1_0 {
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uart {
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sirf,pins = "uart1grp";
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sirf,function = "uart1";
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};
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};
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uart2_pins_a: uart2_0 {
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uart {
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sirf,pins = "uart2grp";
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sirf,function = "uart2";
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};
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};
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uart2_noflow_pins_a: uart2_1 {
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uart {
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sirf,pins = "uart2_nostreamctrlgrp";
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sirf,function = "uart2_nostreamctrl";
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};
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};
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spi0_pins_a: spi0_0 {
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spi {
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sirf,pins = "spi0grp";
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sirf,function = "spi0";
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};
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};
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spi1_pins_a: spi1_0 {
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spi {
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sirf,pins = "spi1grp";
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sirf,function = "spi1";
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};
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};
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i2c0_pins_a: i2c0_0 {
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i2c {
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sirf,pins = "i2c0grp";
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sirf,function = "i2c0";
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};
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};
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i2c1_pins_a: i2c1_0 {
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i2c {
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sirf,pins = "i2c1grp";
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sirf,function = "i2c1";
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};
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};
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pwm0_pins_a: pwm0_0 {
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pwm {
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sirf,pins = "pwm0grp";
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sirf,function = "pwm0";
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};
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};
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pwm1_pins_a: pwm1_0 {
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pwm {
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sirf,pins = "pwm1grp";
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sirf,function = "pwm1";
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};
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};
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pwm2_pins_a: pwm2_0 {
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pwm {
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sirf,pins = "pwm2grp";
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sirf,function = "pwm2";
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};
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};
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pwm3_pins_a: pwm3_0 {
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pwm {
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sirf,pins = "pwm3grp";
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sirf,function = "pwm3";
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};
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};
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gps_pins_a: gps_0 {
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gps {
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sirf,pins = "gpsgrp";
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sirf,function = "gps";
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};
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};
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vip_pins_a: vip_0 {
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vip {
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sirf,pins = "vipgrp";
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sirf,function = "vip";
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};
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};
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sdmmc0_pins_a: sdmmc0_0 {
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sdmmc0 {
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sirf,pins = "sdmmc0grp";
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sirf,function = "sdmmc0";
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};
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};
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sdmmc1_pins_a: sdmmc1_0 {
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sdmmc1 {
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sirf,pins = "sdmmc1grp";
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sirf,function = "sdmmc1";
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};
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};
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sdmmc2_pins_a: sdmmc2_0 {
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sdmmc2 {
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sirf,pins = "sdmmc2grp";
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sirf,function = "sdmmc2";
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};
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};
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sdmmc3_pins_a: sdmmc3_0 {
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sdmmc3 {
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sirf,pins = "sdmmc3grp";
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sirf,function = "sdmmc3";
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};
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};
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sdmmc4_pins_a: sdmmc4_0 {
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sdmmc4 {
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sirf,pins = "sdmmc4grp";
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sirf,function = "sdmmc4";
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};
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};
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sdmmc5_pins_a: sdmmc5_0 {
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sdmmc5 {
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sirf,pins = "sdmmc5grp";
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sirf,function = "sdmmc5";
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};
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};
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i2s_pins_a: i2s_0 {
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i2s {
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sirf,pins = "i2sgrp";
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sirf,function = "i2s";
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};
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};
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ac97_pins_a: ac97_0 {
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ac97 {
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sirf,pins = "ac97grp";
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sirf,function = "ac97";
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};
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};
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nand_pins_a: nand_0 {
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nand {
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sirf,pins = "nandgrp";
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sirf,function = "nand";
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};
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};
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usp0_pins_a: usp0_0 {
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usp0 {
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sirf,pins = "usp0grp";
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sirf,function = "usp0";
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};
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};
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|
usp1_pins_a: usp1_0 {
|
|
usp1 {
|
|
sirf,pins = "usp1grp";
|
|
sirf,function = "usp1";
|
|
};
|
|
};
|
|
usp2_pins_a: usp2_0 {
|
|
usp2 {
|
|
sirf,pins = "usp2grp";
|
|
sirf,function = "usp2";
|
|
};
|
|
};
|
|
usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 {
|
|
usb0_utmi_drvbus {
|
|
sirf,pins = "usb0_utmi_drvbusgrp";
|
|
sirf,function = "usb0_utmi_drvbus";
|
|
};
|
|
};
|
|
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 {
|
|
usb1_utmi_drvbus {
|
|
sirf,pins = "usb1_utmi_drvbusgrp";
|
|
sirf,function = "usb1_utmi_drvbus";
|
|
};
|
|
};
|
|
warm_rst_pins_a: warm_rst_0 {
|
|
warm_rst {
|
|
sirf,pins = "warm_rstgrp";
|
|
sirf,function = "warm_rst";
|
|
};
|
|
};
|
|
pulse_count_pins_a: pulse_count_0 {
|
|
pulse_count {
|
|
sirf,pins = "pulse_countgrp";
|
|
sirf,function = "pulse_count";
|
|
};
|
|
};
|
|
cko0_rst_pins_a: cko0_rst_0 {
|
|
cko0_rst {
|
|
sirf,pins = "cko0_rstgrp";
|
|
sirf,function = "cko0_rst";
|
|
};
|
|
};
|
|
cko1_rst_pins_a: cko1_rst_0 {
|
|
cko1_rst {
|
|
sirf,pins = "cko1_rstgrp";
|
|
sirf,function = "cko1_rst";
|
|
};
|
|
};
|
|
};
|
|
|
|
pwm@cc130000 {
|
|
compatible = "sirf,marco-pwm";
|
|
reg = <0xcc130000 0x10000>;
|
|
};
|
|
|
|
efusesys@cc140000 {
|
|
compatible = "sirf,marco-efuse";
|
|
reg = <0xcc140000 0x10000>;
|
|
};
|
|
|
|
pulsec@cc150000 {
|
|
compatible = "sirf,marco-pulsec";
|
|
reg = <0xcc150000 0x10000>;
|
|
interrupts = <0 48 0>;
|
|
};
|
|
|
|
pci-iobg {
|
|
compatible = "sirf,marco-pciiobg", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0xcd000000 0xcd000000 0x1000000>;
|
|
|
|
sd0: sdhci@cd000000 {
|
|
cell-index = <0>;
|
|
compatible = "sirf,marco-sdhc";
|
|
reg = <0xcd000000 0x100000>;
|
|
interrupts = <0 38 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd1: sdhci@cd100000 {
|
|
cell-index = <1>;
|
|
compatible = "sirf,marco-sdhc";
|
|
reg = <0xcd100000 0x100000>;
|
|
interrupts = <0 38 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd2: sdhci@cd200000 {
|
|
cell-index = <2>;
|
|
compatible = "sirf,marco-sdhc";
|
|
reg = <0xcd200000 0x100000>;
|
|
interrupts = <0 23 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd3: sdhci@cd300000 {
|
|
cell-index = <3>;
|
|
compatible = "sirf,marco-sdhc";
|
|
reg = <0xcd300000 0x100000>;
|
|
interrupts = <0 23 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd4: sdhci@cd400000 {
|
|
cell-index = <4>;
|
|
compatible = "sirf,marco-sdhc";
|
|
reg = <0xcd400000 0x100000>;
|
|
interrupts = <0 39 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd5: sdhci@cd500000 {
|
|
cell-index = <5>;
|
|
compatible = "sirf,marco-sdhc";
|
|
reg = <0xcd500000 0x100000>;
|
|
interrupts = <0 39 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pci-copy@cd900000 {
|
|
compatible = "sirf,marco-pcicp";
|
|
reg = <0xcd900000 0x100000>;
|
|
interrupts = <0 40 0>;
|
|
};
|
|
|
|
rom-interface@cda00000 {
|
|
compatible = "sirf,marco-romif";
|
|
reg = <0xcda00000 0x100000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rtc-iobg {
|
|
compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0xc1000000 0x10000>;
|
|
|
|
gpsrtc@1000 {
|
|
compatible = "sirf,marco-gpsrtc";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <0 55 0>,
|
|
<0 56 0>,
|
|
<0 57 0>;
|
|
};
|
|
|
|
sysrtc@2000 {
|
|
compatible = "sirf,marco-sysrtc";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <0 52 0>,
|
|
<0 53 0>,
|
|
<0 54 0>;
|
|
};
|
|
|
|
pwrc@3000 {
|
|
compatible = "sirf,marco-pwrc";
|
|
reg = <0x3000 0x1000>;
|
|
interrupts = <0 32 0>;
|
|
};
|
|
};
|
|
|
|
uus-iobg {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0xce000000 0xce000000 0x1000000>;
|
|
|
|
usb0: usb@ce000000 {
|
|
compatible = "chipidea,ci13611a-marco";
|
|
reg = <0xce000000 0x10000>;
|
|
interrupts = <0 10 0>;
|
|
};
|
|
|
|
usb1: usb@ce010000 {
|
|
compatible = "chipidea,ci13611a-marco";
|
|
reg = <0xce010000 0x10000>;
|
|
interrupts = <0 11 0>;
|
|
};
|
|
|
|
security@ce020000 {
|
|
compatible = "sirf,marco-security";
|
|
reg = <0xce020000 0x10000>;
|
|
interrupts = <0 42 0>;
|
|
};
|
|
};
|
|
|
|
can-iobg {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0xd0000000 0xd0000000 0x1000000>;
|
|
|
|
can0: can@d0000000 {
|
|
compatible = "sirf,marco-can";
|
|
reg = <0xd0000000 0x10000>;
|
|
};
|
|
|
|
can1: can@d0010000 {
|
|
compatible = "sirf,marco-can";
|
|
reg = <0xd0010000 0x10000>;
|
|
};
|
|
};
|
|
|
|
lvds-iobg {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0xd1000000 0xd1000000 0x1000000>;
|
|
|
|
lvds@d1000000 {
|
|
compatible = "sirf,marco-lvds";
|
|
reg = <0xd1000000 0x10000>;
|
|
interrupts = <0 64 0>;
|
|
};
|
|
};
|
|
};
|
|
};
|