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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 02:05:20 +07:00
df96401649
Currently the driver assumes the register configuration value is identical to its index in the parent map. This patch adds the parent map field in regmap mux clock node which contains the mapping of parent index with actual register configuration value. If regmap node contains this parent map then the configuration value will be taken from this parent map instead of simply writing the index value. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
172 lines
4.1 KiB
C
172 lines
4.1 KiB
C
/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_CLK_RCG_H__
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#define __QCOM_CLK_RCG_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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struct freq_tbl {
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unsigned long freq;
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u8 src;
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u8 pre_div;
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u16 m;
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u16 n;
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};
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/**
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* struct mn - M/N:D counter
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* @mnctr_en_bit: bit to enable mn counter
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* @mnctr_reset_bit: bit to assert mn counter reset
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* @mnctr_mode_shift: lowest bit of mn counter mode field
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* @n_val_shift: lowest bit of n value field
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* @m_val_shift: lowest bit of m value field
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* @width: number of bits in m/n/d values
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* @reset_in_cc: true if the mnctr_reset_bit is in the CC register
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*/
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struct mn {
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u8 mnctr_en_bit;
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u8 mnctr_reset_bit;
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u8 mnctr_mode_shift;
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#define MNCTR_MODE_DUAL 0x2
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#define MNCTR_MODE_MASK 0x3
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u8 n_val_shift;
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u8 m_val_shift;
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u8 width;
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bool reset_in_cc;
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};
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/**
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* struct pre_div - pre-divider
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* @pre_div_shift: lowest bit of pre divider field
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* @pre_div_width: number of bits in predivider
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*/
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struct pre_div {
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u8 pre_div_shift;
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u8 pre_div_width;
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};
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/**
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* struct src_sel - source selector
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* @src_sel_shift: lowest bit of source selection field
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* @parent_map: map from software's parent index to hardware's src_sel field
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*/
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struct src_sel {
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u8 src_sel_shift;
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#define SRC_SEL_MASK 0x7
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const struct parent_map *parent_map;
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};
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/**
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* struct clk_rcg - root clock generator
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*
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* @ns_reg: NS register
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* @md_reg: MD register
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* @mn: mn counter
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* @p: pre divider
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* @s: source selector
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* @freq_tbl: frequency table
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* @clkr: regmap clock handle
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* @lock: register lock
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*
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*/
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struct clk_rcg {
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u32 ns_reg;
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u32 md_reg;
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struct mn mn;
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struct pre_div p;
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struct src_sel s;
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const struct freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_rcg_ops;
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extern const struct clk_ops clk_rcg_bypass_ops;
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extern const struct clk_ops clk_rcg_bypass2_ops;
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extern const struct clk_ops clk_rcg_pixel_ops;
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extern const struct clk_ops clk_rcg_esc_ops;
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extern const struct clk_ops clk_rcg_lcc_ops;
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#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
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/**
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* struct clk_dyn_rcg - root clock generator with glitch free mux
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*
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* @mux_sel_bit: bit to switch glitch free mux
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* @ns_reg: NS0 and NS1 register
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* @md_reg: MD0 and MD1 register
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* @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
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* @mn: mn counter (banked)
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* @s: source selector (banked)
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* @freq_tbl: frequency table
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* @clkr: regmap clock handle
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* @lock: register lock
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*
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*/
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struct clk_dyn_rcg {
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u32 ns_reg[2];
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u32 md_reg[2];
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u32 bank_reg;
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u8 mux_sel_bit;
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struct mn mn[2];
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struct pre_div p[2];
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struct src_sel s[2];
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const struct freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_dyn_rcg_ops;
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#define to_clk_dyn_rcg(_hw) \
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container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
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/**
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* struct clk_rcg2 - root clock generator
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*
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* @cmd_rcgr: corresponds to *_CMD_RCGR
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* @mnd_width: number of bits in m/n/d values
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* @hid_width: number of bits in half integer divider
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* @parent_map: map from software's parent index to hardware's src_sel field
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* @freq_tbl: frequency table
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* @clkr: regmap clock handle
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*
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*/
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struct clk_rcg2 {
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u32 cmd_rcgr;
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u8 mnd_width;
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u8 hid_width;
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const struct parent_map *parent_map;
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const struct freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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};
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#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
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extern const struct clk_ops clk_rcg2_ops;
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extern const struct clk_ops clk_rcg2_floor_ops;
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extern const struct clk_ops clk_edp_pixel_ops;
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extern const struct clk_ops clk_byte_ops;
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extern const struct clk_ops clk_byte2_ops;
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extern const struct clk_ops clk_pixel_ops;
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extern const struct clk_ops clk_gfx3d_ops;
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#endif
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