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e36f561a2c
* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags: Fix IRQ flag handling naming MIPS: Add missing #inclusions of <linux/irq.h> smc91x: Add missing #inclusion of <linux/irq.h> Drop a couple of unnecessary asm/system.h inclusions SH: Add missing consts to sys_execve() declaration Blackfin: Rename IRQ flags handling functions Blackfin: Add missing dep to asm/irqflags.h Blackfin: Rename DES PC2() symbol to avoid collision Blackfin: Split the BF532 BFIN_*_FIO_FLAG() functions to their own header Blackfin: Split PLL code from mach-specific cdef headers
204 lines
6.8 KiB
C
204 lines
6.8 KiB
C
#ifndef _ASM_IA64_SYSTEM_H
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#define _ASM_IA64_SYSTEM_H
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/*
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* System defines. Note that this is included both from .c and .S
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* files, so it does only defines, not any C code. This is based
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* on information published in the Processor Abstraction Layer
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* and the System Abstraction Layer manual.
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*
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* Copyright (C) 1998-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
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* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
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*/
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#include <asm/kregs.h>
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#include <asm/page.h>
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#include <asm/pal.h>
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#include <asm/percpu.h>
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#define GATE_ADDR RGN_BASE(RGN_GATE)
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/*
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* 0xa000000000000000+2*PERCPU_PAGE_SIZE
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* - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
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*/
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#define KERNEL_START (GATE_ADDR+__IA64_UL_CONST(0x100000000))
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#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
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#define LOAD_OFFSET (KERNEL_START - KERNEL_TR_PAGE_SIZE)
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#ifndef __ASSEMBLY__
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#include <linux/kernel.h>
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#include <linux/types.h>
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#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
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struct pci_vector_struct {
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__u16 segment; /* PCI Segment number */
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__u16 bus; /* PCI Bus number */
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__u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
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__u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
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__u32 irq; /* IRQ assigned */
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};
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extern struct ia64_boot_param {
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__u64 command_line; /* physical address of command line arguments */
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__u64 efi_systab; /* physical address of EFI system table */
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__u64 efi_memmap; /* physical address of EFI memory map */
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__u64 efi_memmap_size; /* size of EFI memory map */
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__u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
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__u32 efi_memdesc_version; /* memory descriptor version */
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struct {
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__u16 num_cols; /* number of columns on console output device */
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__u16 num_rows; /* number of rows on console output device */
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__u16 orig_x; /* cursor's x position */
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__u16 orig_y; /* cursor's y position */
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} console_info;
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__u64 fpswa; /* physical address of the fpswa interface */
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__u64 initrd_start;
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__u64 initrd_size;
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} *ia64_boot_param;
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/*
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* Macros to force memory ordering. In these descriptions, "previous"
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* and "subsequent" refer to program order; "visible" means that all
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* architecturally visible effects of a memory access have occurred
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* (at a minimum, this means the memory has been read or written).
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*
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* wmb(): Guarantees that all preceding stores to memory-
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* like regions are visible before any subsequent
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* stores and that all following stores will be
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* visible only after all previous stores.
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* rmb(): Like wmb(), but for reads.
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* mb(): wmb()/rmb() combo, i.e., all previous memory
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* accesses are visible before all subsequent
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* accesses and vice versa. This is also known as
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* a "fence."
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*
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* Note: "mb()" and its variants cannot be used as a fence to order
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* accesses to memory mapped I/O registers. For that, mf.a needs to
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* be used. However, we don't want to always use mf.a because (a)
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* it's (presumably) much slower than mf and (b) mf.a is supported for
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* sequential memory pages only.
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*/
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#define mb() ia64_mf()
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#define rmb() mb()
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#define wmb() mb()
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#define read_barrier_depends() do { } while(0)
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#ifdef CONFIG_SMP
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# define smp_mb() mb()
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# define smp_rmb() rmb()
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# define smp_wmb() wmb()
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# define smp_read_barrier_depends() read_barrier_depends()
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#else
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# define smp_mb() barrier()
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# define smp_rmb() barrier()
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# define smp_wmb() barrier()
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# define smp_read_barrier_depends() do { } while(0)
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#endif
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/*
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* XXX check on this ---I suspect what Linus really wants here is
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* acquire vs release semantics but we can't discuss this stuff with
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* Linus just yet. Grrr...
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*/
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#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
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/*
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* The group barrier in front of the rsm & ssm are necessary to ensure
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* that none of the previous instructions in the same group are
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* affected by the rsm/ssm.
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*/
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#ifdef __KERNEL__
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/*
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* Context switch from one thread to another. If the two threads have
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* different address spaces, schedule() has already taken care of
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* switching to the new address space by calling switch_mm().
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*
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* Disabling access to the fph partition and the debug-register
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* context switch MUST be done before calling ia64_switch_to() since a
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* newly created thread returns directly to
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* ia64_ret_from_syscall_clear_r8.
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*/
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extern struct task_struct *ia64_switch_to (void *next_task);
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struct task_struct;
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extern void ia64_save_extra (struct task_struct *task);
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extern void ia64_load_extra (struct task_struct *task);
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#ifdef CONFIG_VIRT_CPU_ACCOUNTING
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extern void ia64_account_on_switch (struct task_struct *prev, struct task_struct *next);
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# define IA64_ACCOUNT_ON_SWITCH(p,n) ia64_account_on_switch(p,n)
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#else
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# define IA64_ACCOUNT_ON_SWITCH(p,n)
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#endif
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#ifdef CONFIG_PERFMON
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DECLARE_PER_CPU(unsigned long, pfm_syst_info);
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# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
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#else
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# define PERFMON_IS_SYSWIDE() (0)
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#endif
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#define IA64_HAS_EXTRA_STATE(t) \
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((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
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|| PERFMON_IS_SYSWIDE())
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#define __switch_to(prev,next,last) do { \
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IA64_ACCOUNT_ON_SWITCH(prev, next); \
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if (IA64_HAS_EXTRA_STATE(prev)) \
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ia64_save_extra(prev); \
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if (IA64_HAS_EXTRA_STATE(next)) \
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ia64_load_extra(next); \
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ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
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(last) = ia64_switch_to((next)); \
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} while (0)
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#ifdef CONFIG_SMP
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/*
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* In the SMP case, we save the fph state when context-switching away from a thread that
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* modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
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* pick up the state from task->thread.fph, avoiding the complication of having to fetch
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* the latest fph state from another CPU. In other words: eager save, lazy restore.
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*/
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# define switch_to(prev,next,last) do { \
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if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
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ia64_psr(task_pt_regs(prev))->mfh = 0; \
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(prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
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__ia64_save_fpu((prev)->thread.fph); \
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} \
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__switch_to(prev, next, last); \
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/* "next" in old context is "current" in new context */ \
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if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \
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(task_cpu(current) != \
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task_thread_info(current)->last_cpu))) { \
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platform_migrate(current); \
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task_thread_info(current)->last_cpu = task_cpu(current); \
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} \
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} while (0)
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#else
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# define switch_to(prev,next,last) __switch_to(prev, next, last)
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#endif
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#define __ARCH_WANT_UNLOCKED_CTXSW
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#define ARCH_HAS_PREFETCH_SWITCH_STACK
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#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
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void cpu_idle_wait(void);
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#define arch_align_stack(x) (x)
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void default_idle(void);
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_IA64_SYSTEM_H */
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