mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1ae5dc342a
Now that core network takes care of trans_start updates, dont do it in drivers themselves, if possible. Drivers can avoid one cache miss (on dev->trans_start) in their start_xmit() handler. Exceptions are NETIF_F_LLTX drivers Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
992 lines
25 KiB
C
992 lines
25 KiB
C
/*
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* Dave DNET Ethernet Controller driver
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*
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* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
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* Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include "dnet.h"
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#undef DEBUG
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/* function for reading internal MAC register */
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u16 dnet_readw_mac(struct dnet *bp, u16 reg)
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{
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u16 data_read;
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/* issue a read */
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dnet_writel(bp, reg, MACREG_ADDR);
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/* since a read/write op to the MAC is very slow,
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* we must wait before reading the data */
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ndelay(500);
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/* read data read from the MAC register */
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data_read = dnet_readl(bp, MACREG_DATA);
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/* all done */
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return data_read;
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}
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/* function for writing internal MAC register */
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void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val)
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{
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/* load data to write */
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dnet_writel(bp, val, MACREG_DATA);
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/* issue a write */
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dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR);
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/* since a read/write op to the MAC is very slow,
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* we must wait before exiting */
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ndelay(500);
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}
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static void __dnet_set_hwaddr(struct dnet *bp)
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{
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u16 tmp;
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tmp = cpu_to_be16(*((u16 *) bp->dev->dev_addr));
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dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
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tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 2)));
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dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
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tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 4)));
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dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
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}
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static void __devinit dnet_get_hwaddr(struct dnet *bp)
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{
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u16 tmp;
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u8 addr[6];
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/*
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* from MAC docs:
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* "Note that the MAC address is stored in the registers in Hexadecimal
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* form. For example, to set the MAC Address to: AC-DE-48-00-00-80
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* would require writing 0xAC (octet 0) to address 0x0B (high byte of
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* Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of
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* Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of
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* Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of
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* Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of
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* Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of
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* Mac_addr[15:0]).
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*/
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tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG);
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*((u16 *) addr) = be16_to_cpu(tmp);
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tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG);
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*((u16 *) (addr + 2)) = be16_to_cpu(tmp);
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tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG);
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*((u16 *) (addr + 4)) = be16_to_cpu(tmp);
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if (is_valid_ether_addr(addr))
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memcpy(bp->dev->dev_addr, addr, sizeof(addr));
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}
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static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
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{
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struct dnet *bp = bus->priv;
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u16 value;
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while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
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& DNET_INTERNAL_GMII_MNG_CMD_FIN))
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cpu_relax();
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/* only 5 bits allowed for phy-addr and reg_offset */
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mii_id &= 0x1f;
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regnum &= 0x1f;
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/* prepare reg_value for a read */
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value = (mii_id << 8);
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value |= regnum;
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/* write control word */
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dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
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/* wait for end of transfer */
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while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
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& DNET_INTERNAL_GMII_MNG_CMD_FIN))
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cpu_relax();
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value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG);
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pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value);
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return value;
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}
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static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
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u16 value)
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{
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struct dnet *bp = bus->priv;
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u16 tmp;
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pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value);
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while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
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& DNET_INTERNAL_GMII_MNG_CMD_FIN))
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cpu_relax();
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/* prepare for a write operation */
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tmp = (1 << 13);
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/* only 5 bits allowed for phy-addr and reg_offset */
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mii_id &= 0x1f;
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regnum &= 0x1f;
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/* only 16 bits on data */
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value &= 0xffff;
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/* prepare reg_value for a write */
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tmp |= (mii_id << 8);
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tmp |= regnum;
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/* write data to write first */
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dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
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/* write control word */
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dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
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while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG)
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& DNET_INTERNAL_GMII_MNG_CMD_FIN))
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cpu_relax();
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return 0;
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}
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static int dnet_mdio_reset(struct mii_bus *bus)
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{
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return 0;
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}
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static void dnet_handle_link_change(struct net_device *dev)
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{
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struct dnet *bp = netdev_priv(dev);
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struct phy_device *phydev = bp->phy_dev;
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unsigned long flags;
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u32 mode_reg, ctl_reg;
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int status_change = 0;
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spin_lock_irqsave(&bp->lock, flags);
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mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
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ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
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if (phydev->link) {
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if (bp->duplex != phydev->duplex) {
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if (phydev->duplex)
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ctl_reg &=
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~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
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else
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ctl_reg |=
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DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
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bp->duplex = phydev->duplex;
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status_change = 1;
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}
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if (bp->speed != phydev->speed) {
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status_change = 1;
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switch (phydev->speed) {
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case 1000:
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mode_reg |= DNET_INTERNAL_MODE_GBITEN;
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break;
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case 100:
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case 10:
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mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
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break;
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default:
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printk(KERN_WARNING
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"%s: Ack! Speed (%d) is not "
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"10/100/1000!\n", dev->name,
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phydev->speed);
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break;
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}
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bp->speed = phydev->speed;
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}
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}
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if (phydev->link != bp->link) {
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if (phydev->link) {
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mode_reg |=
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(DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
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} else {
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mode_reg &=
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~(DNET_INTERNAL_MODE_RXEN |
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DNET_INTERNAL_MODE_TXEN);
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bp->speed = 0;
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bp->duplex = -1;
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}
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bp->link = phydev->link;
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status_change = 1;
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}
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if (status_change) {
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dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
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dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);
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}
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spin_unlock_irqrestore(&bp->lock, flags);
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if (status_change) {
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if (phydev->link)
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printk(KERN_INFO "%s: link up (%d/%s)\n",
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dev->name, phydev->speed,
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DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
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else
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printk(KERN_INFO "%s: link down\n", dev->name);
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}
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}
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static int dnet_mii_probe(struct net_device *dev)
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{
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struct dnet *bp = netdev_priv(dev);
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struct phy_device *phydev = NULL;
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int phy_addr;
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/* find the first phy */
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for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
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if (bp->mii_bus->phy_map[phy_addr]) {
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phydev = bp->mii_bus->phy_map[phy_addr];
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break;
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}
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}
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if (!phydev) {
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printk(KERN_ERR "%s: no PHY found\n", dev->name);
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return -ENODEV;
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}
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/* TODO : add pin_irq */
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/* attach the mac to the phy */
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if (bp->capabilities & DNET_HAS_RMII) {
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phydev = phy_connect(dev, dev_name(&phydev->dev),
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&dnet_handle_link_change, 0,
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PHY_INTERFACE_MODE_RMII);
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} else {
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phydev = phy_connect(dev, dev_name(&phydev->dev),
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&dnet_handle_link_change, 0,
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PHY_INTERFACE_MODE_MII);
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}
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if (IS_ERR(phydev)) {
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printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
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return PTR_ERR(phydev);
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}
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/* mask with MAC supported features */
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if (bp->capabilities & DNET_HAS_GIGABIT)
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phydev->supported &= PHY_GBIT_FEATURES;
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else
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phydev->supported &= PHY_BASIC_FEATURES;
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phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
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phydev->advertising = phydev->supported;
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bp->link = 0;
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bp->speed = 0;
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bp->duplex = -1;
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bp->phy_dev = phydev;
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return 0;
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}
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static int dnet_mii_init(struct dnet *bp)
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{
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int err, i;
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bp->mii_bus = mdiobus_alloc();
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if (bp->mii_bus == NULL)
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return -ENOMEM;
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bp->mii_bus->name = "dnet_mii_bus";
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bp->mii_bus->read = &dnet_mdio_read;
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bp->mii_bus->write = &dnet_mdio_write;
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bp->mii_bus->reset = &dnet_mdio_reset;
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snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
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bp->mii_bus->priv = bp;
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bp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
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if (!bp->mii_bus->irq) {
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err = -ENOMEM;
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goto err_out;
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}
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for (i = 0; i < PHY_MAX_ADDR; i++)
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bp->mii_bus->irq[i] = PHY_POLL;
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platform_set_drvdata(bp->dev, bp->mii_bus);
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if (mdiobus_register(bp->mii_bus)) {
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err = -ENXIO;
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goto err_out_free_mdio_irq;
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}
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if (dnet_mii_probe(bp->dev) != 0) {
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err = -ENXIO;
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goto err_out_unregister_bus;
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}
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return 0;
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err_out_unregister_bus:
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mdiobus_unregister(bp->mii_bus);
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err_out_free_mdio_irq:
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kfree(bp->mii_bus->irq);
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err_out:
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mdiobus_free(bp->mii_bus);
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return err;
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}
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/* For Neptune board: LINK1000 as Link LED and TX as activity LED */
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int dnet_phy_marvell_fixup(struct phy_device *phydev)
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{
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return phy_write(phydev, 0x18, 0x4148);
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}
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static void dnet_update_stats(struct dnet *bp)
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{
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u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT;
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u32 *p = &bp->hw_stats.rx_pkt_ignr;
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u32 *end = &bp->hw_stats.rx_byte + 1;
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WARN_ON((unsigned long)(end - p - 1) !=
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(DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4);
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for (; p < end; p++, reg++)
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*p += readl(reg);
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reg = bp->regs + DNET_TX_UNICAST_CNT;
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p = &bp->hw_stats.tx_unicast;
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end = &bp->hw_stats.tx_byte + 1;
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WARN_ON((unsigned long)(end - p - 1) !=
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(DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4);
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for (; p < end; p++, reg++)
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*p += readl(reg);
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}
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static int dnet_poll(struct napi_struct *napi, int budget)
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{
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struct dnet *bp = container_of(napi, struct dnet, napi);
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struct net_device *dev = bp->dev;
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int npackets = 0;
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unsigned int pkt_len;
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struct sk_buff *skb;
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unsigned int *data_ptr;
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u32 int_enable;
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u32 cmd_word;
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int i;
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while (npackets < budget) {
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/*
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* break out of while loop if there are no more
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* packets waiting
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*/
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if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) {
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napi_complete(napi);
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int_enable = dnet_readl(bp, INTR_ENB);
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int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
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dnet_writel(bp, int_enable, INTR_ENB);
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return 0;
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}
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cmd_word = dnet_readl(bp, RX_LEN_FIFO);
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pkt_len = cmd_word & 0xFFFF;
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if (cmd_word & 0xDF180000)
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printk(KERN_ERR "%s packet receive error %x\n",
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__func__, cmd_word);
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skb = dev_alloc_skb(pkt_len + 5);
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if (skb != NULL) {
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/* Align IP on 16 byte boundaries */
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skb_reserve(skb, 2);
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/*
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* 'skb_put()' points to the start of sk_buff
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* data area.
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*/
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data_ptr = (unsigned int *)skb_put(skb, pkt_len);
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for (i = 0; i < (pkt_len + 3) >> 2; i++)
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*data_ptr++ = dnet_readl(bp, RX_DATA_FIFO);
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skb->protocol = eth_type_trans(skb, dev);
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netif_receive_skb(skb);
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npackets++;
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} else
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printk(KERN_NOTICE
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"%s: No memory to allocate a sk_buff of "
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"size %u.\n", dev->name, pkt_len);
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}
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budget -= npackets;
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if (npackets < budget) {
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/* We processed all packets available. Tell NAPI it can
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* stop polling then re-enable rx interrupts */
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napi_complete(napi);
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int_enable = dnet_readl(bp, INTR_ENB);
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int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF;
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dnet_writel(bp, int_enable, INTR_ENB);
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return 0;
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}
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/* There are still packets waiting */
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return 1;
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}
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static irqreturn_t dnet_interrupt(int irq, void *dev_id)
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{
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struct net_device *dev = dev_id;
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struct dnet *bp = netdev_priv(dev);
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u32 int_src, int_enable, int_current;
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unsigned long flags;
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unsigned int handled = 0;
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spin_lock_irqsave(&bp->lock, flags);
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/* read and clear the DNET irq (clear on read) */
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int_src = dnet_readl(bp, INTR_SRC);
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int_enable = dnet_readl(bp, INTR_ENB);
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int_current = int_src & int_enable;
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/* restart the queue if we had stopped it for TX fifo almost full */
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if (int_current & DNET_INTR_SRC_TX_FIFOAE) {
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int_enable = dnet_readl(bp, INTR_ENB);
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int_enable &= ~DNET_INTR_ENB_TX_FIFOAE;
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dnet_writel(bp, int_enable, INTR_ENB);
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netif_wake_queue(dev);
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handled = 1;
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}
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/* RX FIFO error checking */
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if (int_current &
|
|
(DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) {
|
|
printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__,
|
|
dnet_readl(bp, RX_STATUS), int_current);
|
|
/* we can only flush the RX FIFOs */
|
|
dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL);
|
|
ndelay(500);
|
|
dnet_writel(bp, 0, SYS_CTL);
|
|
handled = 1;
|
|
}
|
|
|
|
/* TX FIFO error checking */
|
|
if (int_current &
|
|
(DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) {
|
|
printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__,
|
|
dnet_readl(bp, TX_STATUS), int_current);
|
|
/* we can only flush the TX FIFOs */
|
|
dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL);
|
|
ndelay(500);
|
|
dnet_writel(bp, 0, SYS_CTL);
|
|
handled = 1;
|
|
}
|
|
|
|
if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) {
|
|
if (napi_schedule_prep(&bp->napi)) {
|
|
/*
|
|
* There's no point taking any more interrupts
|
|
* until we have processed the buffers
|
|
*/
|
|
/* Disable Rx interrupts and schedule NAPI poll */
|
|
int_enable = dnet_readl(bp, INTR_ENB);
|
|
int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF;
|
|
dnet_writel(bp, int_enable, INTR_ENB);
|
|
__napi_schedule(&bp->napi);
|
|
}
|
|
handled = 1;
|
|
}
|
|
|
|
if (!handled)
|
|
pr_debug("%s: irq %x remains\n", __func__, int_current);
|
|
|
|
spin_unlock_irqrestore(&bp->lock, flags);
|
|
|
|
return IRQ_RETVAL(handled);
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
static inline void dnet_print_skb(struct sk_buff *skb)
|
|
{
|
|
int k;
|
|
printk(KERN_DEBUG PFX "data:");
|
|
for (k = 0; k < skb->len; k++)
|
|
printk(" %02x", (unsigned int)skb->data[k]);
|
|
printk("\n");
|
|
}
|
|
#else
|
|
#define dnet_print_skb(skb) do {} while (0)
|
|
#endif
|
|
|
|
static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
|
|
struct dnet *bp = netdev_priv(dev);
|
|
u32 tx_status, irq_enable;
|
|
unsigned int len, i, tx_cmd, wrsz;
|
|
unsigned long flags;
|
|
unsigned int *bufp;
|
|
|
|
tx_status = dnet_readl(bp, TX_STATUS);
|
|
|
|
pr_debug("start_xmit: len %u head %p data %p\n",
|
|
skb->len, skb->head, skb->data);
|
|
dnet_print_skb(skb);
|
|
|
|
/* frame size (words) */
|
|
len = (skb->len + 3) >> 2;
|
|
|
|
spin_lock_irqsave(&bp->lock, flags);
|
|
|
|
tx_status = dnet_readl(bp, TX_STATUS);
|
|
|
|
bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL);
|
|
wrsz = (u32) skb->len + 3;
|
|
wrsz += ((unsigned long) skb->data) & 0x3;
|
|
wrsz >>= 2;
|
|
tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len;
|
|
|
|
/* check if there is enough room for the current frame */
|
|
if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) {
|
|
for (i = 0; i < wrsz; i++)
|
|
dnet_writel(bp, *bufp++, TX_DATA_FIFO);
|
|
|
|
/*
|
|
* inform MAC that a packet's written and ready to be
|
|
* shipped out
|
|
*/
|
|
dnet_writel(bp, tx_cmd, TX_LEN_FIFO);
|
|
}
|
|
|
|
if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) {
|
|
netif_stop_queue(dev);
|
|
tx_status = dnet_readl(bp, INTR_SRC);
|
|
irq_enable = dnet_readl(bp, INTR_ENB);
|
|
irq_enable |= DNET_INTR_ENB_TX_FIFOAE;
|
|
dnet_writel(bp, irq_enable, INTR_ENB);
|
|
}
|
|
|
|
/* free the buffer */
|
|
dev_kfree_skb(skb);
|
|
|
|
spin_unlock_irqrestore(&bp->lock, flags);
|
|
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
static void dnet_reset_hw(struct dnet *bp)
|
|
{
|
|
/* put ts_mac in IDLE state i.e. disable rx/tx */
|
|
dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN);
|
|
|
|
/*
|
|
* RX FIFO almost full threshold: only cmd FIFO almost full is
|
|
* implemented for RX side
|
|
*/
|
|
dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH);
|
|
/*
|
|
* TX FIFO almost empty threshold: only data FIFO almost empty
|
|
* is implemented for TX side
|
|
*/
|
|
dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH);
|
|
|
|
/* flush rx/tx fifos */
|
|
dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
|
|
SYS_CTL);
|
|
msleep(1);
|
|
dnet_writel(bp, 0, SYS_CTL);
|
|
}
|
|
|
|
static void dnet_init_hw(struct dnet *bp)
|
|
{
|
|
u32 config;
|
|
|
|
dnet_reset_hw(bp);
|
|
__dnet_set_hwaddr(bp);
|
|
|
|
config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
|
|
|
|
if (bp->dev->flags & IFF_PROMISC)
|
|
/* Copy All Frames */
|
|
config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC;
|
|
if (!(bp->dev->flags & IFF_BROADCAST))
|
|
/* No BroadCast */
|
|
config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST;
|
|
|
|
config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
|
|
DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
|
|
DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
|
|
DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
|
|
|
|
dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config);
|
|
|
|
/* clear irq before enabling them */
|
|
config = dnet_readl(bp, INTR_SRC);
|
|
|
|
/* enable RX/TX interrupt, recv packet ready interrupt */
|
|
dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY |
|
|
DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR |
|
|
DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL |
|
|
DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM |
|
|
DNET_INTR_ENB_RX_PKTRDY, INTR_ENB);
|
|
}
|
|
|
|
static int dnet_open(struct net_device *dev)
|
|
{
|
|
struct dnet *bp = netdev_priv(dev);
|
|
|
|
/* if the phy is not yet register, retry later */
|
|
if (!bp->phy_dev)
|
|
return -EAGAIN;
|
|
|
|
if (!is_valid_ether_addr(dev->dev_addr))
|
|
return -EADDRNOTAVAIL;
|
|
|
|
napi_enable(&bp->napi);
|
|
dnet_init_hw(bp);
|
|
|
|
phy_start_aneg(bp->phy_dev);
|
|
|
|
/* schedule a link state check */
|
|
phy_start(bp->phy_dev);
|
|
|
|
netif_start_queue(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dnet_close(struct net_device *dev)
|
|
{
|
|
struct dnet *bp = netdev_priv(dev);
|
|
|
|
netif_stop_queue(dev);
|
|
napi_disable(&bp->napi);
|
|
|
|
if (bp->phy_dev)
|
|
phy_stop(bp->phy_dev);
|
|
|
|
dnet_reset_hw(bp);
|
|
netif_carrier_off(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat)
|
|
{
|
|
pr_debug("%s\n", __func__);
|
|
pr_debug("----------------------------- RX statistics "
|
|
"-------------------------------\n");
|
|
pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr);
|
|
pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err);
|
|
pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm);
|
|
pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm);
|
|
pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol);
|
|
pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err);
|
|
pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt);
|
|
pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm);
|
|
pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm);
|
|
pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast);
|
|
pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast);
|
|
pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag);
|
|
pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink);
|
|
pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib);
|
|
pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd);
|
|
pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte);
|
|
pr_debug("----------------------------- TX statistics "
|
|
"-------------------------------\n");
|
|
pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast);
|
|
pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm);
|
|
pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast);
|
|
pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast);
|
|
pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag);
|
|
pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs);
|
|
pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo);
|
|
pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte);
|
|
}
|
|
|
|
static struct net_device_stats *dnet_get_stats(struct net_device *dev)
|
|
{
|
|
|
|
struct dnet *bp = netdev_priv(dev);
|
|
struct net_device_stats *nstat = &dev->stats;
|
|
struct dnet_stats *hwstat = &bp->hw_stats;
|
|
|
|
/* read stats from hardware */
|
|
dnet_update_stats(bp);
|
|
|
|
/* Convert HW stats into netdevice stats */
|
|
nstat->rx_errors = (hwstat->rx_len_chk_err +
|
|
hwstat->rx_lng_frm + hwstat->rx_shrt_frm +
|
|
/* ignore IGP violation error
|
|
hwstat->rx_ipg_viol + */
|
|
hwstat->rx_crc_err +
|
|
hwstat->rx_pre_shrink +
|
|
hwstat->rx_drib_nib + hwstat->rx_unsup_opcd);
|
|
nstat->tx_errors = hwstat->tx_bad_fcs;
|
|
nstat->rx_length_errors = (hwstat->rx_len_chk_err +
|
|
hwstat->rx_lng_frm +
|
|
hwstat->rx_shrt_frm + hwstat->rx_pre_shrink);
|
|
nstat->rx_crc_errors = hwstat->rx_crc_err;
|
|
nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib;
|
|
nstat->rx_packets = hwstat->rx_ok_pkt;
|
|
nstat->tx_packets = (hwstat->tx_unicast +
|
|
hwstat->tx_multicast + hwstat->tx_brdcast);
|
|
nstat->rx_bytes = hwstat->rx_byte;
|
|
nstat->tx_bytes = hwstat->tx_byte;
|
|
nstat->multicast = hwstat->rx_multicast;
|
|
nstat->rx_missed_errors = hwstat->rx_pkt_ignr;
|
|
|
|
dnet_print_pretty_hwstats(hwstat);
|
|
|
|
return nstat;
|
|
}
|
|
|
|
static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
{
|
|
struct dnet *bp = netdev_priv(dev);
|
|
struct phy_device *phydev = bp->phy_dev;
|
|
|
|
if (!phydev)
|
|
return -ENODEV;
|
|
|
|
return phy_ethtool_gset(phydev, cmd);
|
|
}
|
|
|
|
static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
{
|
|
struct dnet *bp = netdev_priv(dev);
|
|
struct phy_device *phydev = bp->phy_dev;
|
|
|
|
if (!phydev)
|
|
return -ENODEV;
|
|
|
|
return phy_ethtool_sset(phydev, cmd);
|
|
}
|
|
|
|
static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
|
|
{
|
|
struct dnet *bp = netdev_priv(dev);
|
|
struct phy_device *phydev = bp->phy_dev;
|
|
|
|
if (!netif_running(dev))
|
|
return -EINVAL;
|
|
|
|
if (!phydev)
|
|
return -ENODEV;
|
|
|
|
return phy_mii_ioctl(phydev, if_mii(rq), cmd);
|
|
}
|
|
|
|
static void dnet_get_drvinfo(struct net_device *dev,
|
|
struct ethtool_drvinfo *info)
|
|
{
|
|
strcpy(info->driver, DRV_NAME);
|
|
strcpy(info->version, DRV_VERSION);
|
|
strcpy(info->bus_info, "0");
|
|
}
|
|
|
|
static const struct ethtool_ops dnet_ethtool_ops = {
|
|
.get_settings = dnet_get_settings,
|
|
.set_settings = dnet_set_settings,
|
|
.get_drvinfo = dnet_get_drvinfo,
|
|
.get_link = ethtool_op_get_link,
|
|
};
|
|
|
|
static const struct net_device_ops dnet_netdev_ops = {
|
|
.ndo_open = dnet_open,
|
|
.ndo_stop = dnet_close,
|
|
.ndo_get_stats = dnet_get_stats,
|
|
.ndo_start_xmit = dnet_start_xmit,
|
|
.ndo_do_ioctl = dnet_ioctl,
|
|
.ndo_set_mac_address = eth_mac_addr,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
.ndo_change_mtu = eth_change_mtu,
|
|
};
|
|
|
|
static int __devinit dnet_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
struct net_device *dev;
|
|
struct dnet *bp;
|
|
struct phy_device *phydev;
|
|
int err = -ENXIO;
|
|
unsigned int mem_base, mem_size, irq;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "no mmio resource defined\n");
|
|
goto err_out;
|
|
}
|
|
mem_base = res->start;
|
|
mem_size = resource_size(res);
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (!request_mem_region(mem_base, mem_size, DRV_NAME)) {
|
|
dev_err(&pdev->dev, "no memory region available\n");
|
|
err = -EBUSY;
|
|
goto err_out;
|
|
}
|
|
|
|
err = -ENOMEM;
|
|
dev = alloc_etherdev(sizeof(*bp));
|
|
if (!dev) {
|
|
dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
|
|
goto err_out;
|
|
}
|
|
|
|
/* TODO: Actually, we have some interesting features... */
|
|
dev->features |= 0;
|
|
|
|
bp = netdev_priv(dev);
|
|
bp->dev = dev;
|
|
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
spin_lock_init(&bp->lock);
|
|
|
|
bp->regs = ioremap(mem_base, mem_size);
|
|
if (!bp->regs) {
|
|
dev_err(&pdev->dev, "failed to map registers, aborting.\n");
|
|
err = -ENOMEM;
|
|
goto err_out_free_dev;
|
|
}
|
|
|
|
dev->irq = irq;
|
|
err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
|
|
irq, err);
|
|
goto err_out_iounmap;
|
|
}
|
|
|
|
dev->netdev_ops = &dnet_netdev_ops;
|
|
netif_napi_add(dev, &bp->napi, dnet_poll, 64);
|
|
dev->ethtool_ops = &dnet_ethtool_ops;
|
|
|
|
dev->base_addr = (unsigned long)bp->regs;
|
|
|
|
bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK;
|
|
|
|
dnet_get_hwaddr(bp);
|
|
|
|
if (!is_valid_ether_addr(dev->dev_addr)) {
|
|
/* choose a random ethernet address */
|
|
random_ether_addr(dev->dev_addr);
|
|
__dnet_set_hwaddr(bp);
|
|
}
|
|
|
|
err = register_netdev(dev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
|
|
goto err_out_free_irq;
|
|
}
|
|
|
|
/* register the PHY board fixup (for Marvell 88E1111) */
|
|
err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0,
|
|
dnet_phy_marvell_fixup);
|
|
/* we can live without it, so just issue a warning */
|
|
if (err)
|
|
dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n");
|
|
|
|
if (dnet_mii_init(bp) != 0)
|
|
goto err_out_unregister_netdev;
|
|
|
|
dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n",
|
|
bp->regs, mem_base, dev->irq, dev->dev_addr);
|
|
dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n",
|
|
(bp->capabilities & DNET_HAS_MDIO) ? "" : "no ",
|
|
(bp->capabilities & DNET_HAS_IRQ) ? "" : "no ",
|
|
(bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ",
|
|
(bp->capabilities & DNET_HAS_DMA) ? "" : "no ");
|
|
phydev = bp->phy_dev;
|
|
dev_info(&pdev->dev, "attached PHY driver [%s] "
|
|
"(mii_bus:phy_addr=%s, irq=%d)\n",
|
|
phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
|
|
|
|
return 0;
|
|
|
|
err_out_unregister_netdev:
|
|
unregister_netdev(dev);
|
|
err_out_free_irq:
|
|
free_irq(dev->irq, dev);
|
|
err_out_iounmap:
|
|
iounmap(bp->regs);
|
|
err_out_free_dev:
|
|
free_netdev(dev);
|
|
err_out:
|
|
return err;
|
|
}
|
|
|
|
static int __devexit dnet_remove(struct platform_device *pdev)
|
|
{
|
|
|
|
struct net_device *dev;
|
|
struct dnet *bp;
|
|
|
|
dev = platform_get_drvdata(pdev);
|
|
|
|
if (dev) {
|
|
bp = netdev_priv(dev);
|
|
if (bp->phy_dev)
|
|
phy_disconnect(bp->phy_dev);
|
|
mdiobus_unregister(bp->mii_bus);
|
|
kfree(bp->mii_bus->irq);
|
|
mdiobus_free(bp->mii_bus);
|
|
unregister_netdev(dev);
|
|
free_irq(dev->irq, dev);
|
|
iounmap(bp->regs);
|
|
free_netdev(dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver dnet_driver = {
|
|
.probe = dnet_probe,
|
|
.remove = __devexit_p(dnet_remove),
|
|
.driver = {
|
|
.name = "dnet",
|
|
},
|
|
};
|
|
|
|
static int __init dnet_init(void)
|
|
{
|
|
return platform_driver_register(&dnet_driver);
|
|
}
|
|
|
|
static void __exit dnet_exit(void)
|
|
{
|
|
platform_driver_unregister(&dnet_driver);
|
|
}
|
|
|
|
module_init(dnet_init);
|
|
module_exit(dnet_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Dave DNET Ethernet driver");
|
|
MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, "
|
|
"Matteo Vit <matteo.vit@dave.eu>");
|