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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6c9da387c8
The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/*
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* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __DTS_HI3519_CLOCK_H
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#define __DTS_HI3519_CLOCK_H
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#define HI3519_FMC_CLK 1
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#define HI3519_SPI0_CLK 2
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#define HI3519_SPI1_CLK 3
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#define HI3519_SPI2_CLK 4
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#define HI3519_UART0_CLK 5
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#define HI3519_UART1_CLK 6
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#define HI3519_UART2_CLK 7
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#define HI3519_UART3_CLK 8
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#define HI3519_UART4_CLK 9
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#define HI3519_PWM_CLK 10
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#define HI3519_DMA_CLK 11
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#define HI3519_IR_CLK 12
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#define HI3519_ETH_PHY_CLK 13
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#define HI3519_ETH_MAC_CLK 14
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#define HI3519_ETH_MACIF_CLK 15
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#define HI3519_USB2_BUS_CLK 16
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#define HI3519_USB2_PORT_CLK 17
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#define HI3519_USB3_CLK 18
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#endif /* __DTS_HI3519_CLOCK_H */
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