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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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253b0887b3
This moves out the old legacy CPG clocks to their own file, and converts over the existing users. With these clocks going away and each CPU dealing with them on their own, CPUs can gradually move over to the new interface. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
172 lines
3.7 KiB
C
172 lines
3.7 KiB
C
/*
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* arch/sh/kernel/cpu/sh4/clock-sh4-202.c
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*
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* Additional SH4-202 support for the clock framework
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*
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* Copyright (C) 2005 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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#define CPG2_FRQCR3 0xfe0a0018
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static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 };
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static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 };
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static unsigned long emi_clk_recalc(struct clk *clk)
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{
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int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007;
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return clk->parent->rate / frqcr3_divisors[idx];
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}
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static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
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{
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int divisor = clk->parent->rate / rate;
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int i;
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for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++)
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if (frqcr3_divisors[i] == divisor)
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return frqcr3_values[i];
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/* Safe fallback */
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return 5;
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}
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static struct clk_ops sh4202_emi_clk_ops = {
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.recalc = emi_clk_recalc,
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};
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static struct clk sh4202_emi_clk = {
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.name = "emi_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh4202_emi_clk_ops,
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};
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static unsigned long femi_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007;
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return clk->parent->rate / frqcr3_divisors[idx];
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}
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static struct clk_ops sh4202_femi_clk_ops = {
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.recalc = femi_clk_recalc,
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};
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static struct clk sh4202_femi_clk = {
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.name = "femi_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh4202_femi_clk_ops,
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};
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static void shoc_clk_init(struct clk *clk)
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{
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int i;
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/*
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* For some reason, the shoc_clk seems to be set to some really
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* insane value at boot (values outside of the allowable frequency
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* range for instance). We deal with this by scaling it back down
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* to something sensible just in case.
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*
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* Start scaling from the high end down until we find something
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* that passes rate verification..
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*/
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for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
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int divisor = frqcr3_divisors[i];
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if (clk->ops->set_rate(clk, clk->parent->rate /
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divisor, 0) == 0)
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break;
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}
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WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */
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}
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static unsigned long shoc_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007;
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return clk->parent->rate / frqcr3_divisors[idx];
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}
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static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *bclk = clk_get(NULL, "bus_clk");
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unsigned long bclk_rate = clk_get_rate(bclk);
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clk_put(bclk);
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if (rate > bclk_rate)
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return 1;
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if (rate > 66000000)
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return 1;
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return 0;
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}
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static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
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{
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unsigned long frqcr3;
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unsigned int tmp;
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/* Make sure we have something sensible to switch to */
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if (shoc_clk_verify_rate(clk, rate) != 0)
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return -EINVAL;
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tmp = frqcr3_lookup(clk, rate);
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frqcr3 = ctrl_inl(CPG2_FRQCR3);
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frqcr3 &= ~(0x0007 << 6);
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frqcr3 |= tmp << 6;
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ctrl_outl(frqcr3, CPG2_FRQCR3);
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clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
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return 0;
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}
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static struct clk_ops sh4202_shoc_clk_ops = {
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.init = shoc_clk_init,
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.recalc = shoc_clk_recalc,
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.set_rate = shoc_clk_set_rate,
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};
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static struct clk sh4202_shoc_clk = {
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.name = "shoc_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh4202_shoc_clk_ops,
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};
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static struct clk *sh4202_onchip_clocks[] = {
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&sh4202_emi_clk,
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&sh4202_femi_clk,
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&sh4202_shoc_clk,
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};
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int __init arch_clk_init(void)
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{
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
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struct clk *clkp = sh4202_onchip_clocks[i];
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clkp->parent = clk;
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ret |= clk_register(clkp);
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}
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clk_put(clk);
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return ret;
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}
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