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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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da3ceae4ec
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by having a dedicate tree for each core similar to the CPU0 tree. Like the DSU tree, a supplementaty mux has been added to use the CPU0 frequency instead. But since the cluster only has a single power rail and shares a single PLL, it's not worth adding 3 unsused clock tree, so we add only the mux to select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores. They are set read-only because the early boot stages sets them to select the CPU0 input clock. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
265 lines
8.5 KiB
C
265 lines
8.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2016 Amlogic, Inc.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* Copyright (c) 2018 Amlogic, inc.
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* Author: Qiufang Dai <qiufang.dai@amlogic.com>
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* Author: Jian Hu <jian.hu@amlogic.com>
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*
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*/
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#ifndef __G12A_H
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#define __G12A_H
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/*
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* Clock controller register offsets
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*
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* Register offsets from the data sheet must be multiplied by 4 before
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* adding them to the base address to get the right value.
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*/
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#define HHI_MIPI_CNTL0 0x000
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#define HHI_MIPI_CNTL1 0x004
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#define HHI_MIPI_CNTL2 0x008
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#define HHI_MIPI_STS 0x00C
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#define HHI_GP0_PLL_CNTL0 0x040
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#define HHI_GP0_PLL_CNTL1 0x044
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#define HHI_GP0_PLL_CNTL2 0x048
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#define HHI_GP0_PLL_CNTL3 0x04C
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#define HHI_GP0_PLL_CNTL4 0x050
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#define HHI_GP0_PLL_CNTL5 0x054
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#define HHI_GP0_PLL_CNTL6 0x058
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#define HHI_GP0_PLL_STS 0x05C
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#define HHI_GP1_PLL_CNTL0 0x060
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#define HHI_GP1_PLL_CNTL1 0x064
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#define HHI_GP1_PLL_CNTL2 0x068
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#define HHI_GP1_PLL_CNTL3 0x06C
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#define HHI_GP1_PLL_CNTL4 0x070
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#define HHI_GP1_PLL_CNTL5 0x074
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#define HHI_GP1_PLL_CNTL6 0x078
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#define HHI_GP1_PLL_STS 0x07C
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#define HHI_PCIE_PLL_CNTL0 0x098
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#define HHI_PCIE_PLL_CNTL1 0x09C
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#define HHI_PCIE_PLL_CNTL2 0x0A0
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#define HHI_PCIE_PLL_CNTL3 0x0A4
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#define HHI_PCIE_PLL_CNTL4 0x0A8
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#define HHI_PCIE_PLL_CNTL5 0x0AC
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#define HHI_PCIE_PLL_STS 0x0B8
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#define HHI_HIFI_PLL_CNTL0 0x0D8
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#define HHI_HIFI_PLL_CNTL1 0x0DC
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#define HHI_HIFI_PLL_CNTL2 0x0E0
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#define HHI_HIFI_PLL_CNTL3 0x0E4
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#define HHI_HIFI_PLL_CNTL4 0x0E8
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#define HHI_HIFI_PLL_CNTL5 0x0EC
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#define HHI_HIFI_PLL_CNTL6 0x0F0
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#define HHI_VIID_CLK_DIV 0x128
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#define HHI_VIID_CLK_CNTL 0x12C
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#define HHI_GCLK_MPEG0 0x140
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#define HHI_GCLK_MPEG1 0x144
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#define HHI_GCLK_MPEG2 0x148
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#define HHI_GCLK_OTHER 0x150
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#define HHI_GCLK_OTHER2 0x154
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c
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#define HHI_VID_CLK_DIV 0x164
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#define HHI_MPEG_CLK_CNTL 0x174
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#define HHI_AUD_CLK_CNTL 0x178
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#define HHI_VID_CLK_CNTL 0x17c
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#define HHI_TS_CLK_CNTL 0x190
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#define HHI_VID_CLK_CNTL2 0x194
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c
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#define HHI_VID_PLL_CLK_DIV 0x1A0
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#define HHI_MALI_CLK_CNTL 0x1b0
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#define HHI_VPU_CLKC_CNTL 0x1b4
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#define HHI_VPU_CLK_CNTL 0x1bC
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#define HHI_HDMI_CLK_CNTL 0x1CC
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#define HHI_VDEC_CLK_CNTL 0x1E0
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#define HHI_VDEC2_CLK_CNTL 0x1E4
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#define HHI_VDEC3_CLK_CNTL 0x1E8
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#define HHI_VDEC4_CLK_CNTL 0x1EC
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#define HHI_HDCP22_CLK_CNTL 0x1F0
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#define HHI_VAPBCLK_CNTL 0x1F4
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#define HHI_SYS_CPUB_CLK_CNTL1 0x200
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#define HHI_SYS_CPUB_CLK_CNTL 0x208
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#define HHI_VPU_CLKB_CNTL 0x20C
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#define HHI_SYS_CPU_CLK_CNTL2 0x210
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#define HHI_SYS_CPU_CLK_CNTL3 0x214
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#define HHI_SYS_CPU_CLK_CNTL4 0x218
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#define HHI_SYS_CPU_CLK_CNTL5 0x21c
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#define HHI_SYS_CPU_CLK_CNTL6 0x220
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#define HHI_GEN_CLK_CNTL 0x228
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#define HHI_VDIN_MEAS_CLK_CNTL 0x250
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#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
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#define HHI_NAND_CLK_CNTL 0x25C
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#define HHI_SD_EMMC_CLK_CNTL 0x264
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#define HHI_MPLL_CNTL0 0x278
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#define HHI_MPLL_CNTL1 0x27C
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#define HHI_MPLL_CNTL2 0x280
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#define HHI_MPLL_CNTL3 0x284
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#define HHI_MPLL_CNTL4 0x288
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#define HHI_MPLL_CNTL5 0x28c
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#define HHI_MPLL_CNTL6 0x290
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#define HHI_MPLL_CNTL7 0x294
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#define HHI_MPLL_CNTL8 0x298
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#define HHI_FIX_PLL_CNTL0 0x2A0
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#define HHI_FIX_PLL_CNTL1 0x2A4
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#define HHI_FIX_PLL_CNTL3 0x2AC
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#define HHI_SYS_PLL_CNTL0 0x2f4
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#define HHI_SYS_PLL_CNTL1 0x2f8
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#define HHI_SYS_PLL_CNTL2 0x2fc
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#define HHI_SYS_PLL_CNTL3 0x300
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#define HHI_SYS_PLL_CNTL4 0x304
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#define HHI_SYS_PLL_CNTL5 0x308
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#define HHI_SYS_PLL_CNTL6 0x30c
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#define HHI_HDMI_PLL_CNTL0 0x320
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#define HHI_HDMI_PLL_CNTL1 0x324
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#define HHI_HDMI_PLL_CNTL2 0x328
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#define HHI_HDMI_PLL_CNTL3 0x32c
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#define HHI_HDMI_PLL_CNTL4 0x330
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#define HHI_HDMI_PLL_CNTL5 0x334
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#define HHI_HDMI_PLL_CNTL6 0x338
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#define HHI_SPICC_CLK_CNTL 0x3dc
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#define HHI_SYS1_PLL_CNTL0 0x380
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#define HHI_SYS1_PLL_CNTL1 0x384
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#define HHI_SYS1_PLL_CNTL2 0x388
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#define HHI_SYS1_PLL_CNTL3 0x38c
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#define HHI_SYS1_PLL_CNTL4 0x390
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#define HHI_SYS1_PLL_CNTL5 0x394
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#define HHI_SYS1_PLL_CNTL6 0x398
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/*
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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#define CLKID_MPEG_SEL 8
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#define CLKID_MPEG_DIV 9
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#define CLKID_SD_EMMC_A_CLK0_SEL 63
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#define CLKID_SD_EMMC_A_CLK0_DIV 64
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#define CLKID_SD_EMMC_B_CLK0_SEL 65
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#define CLKID_SD_EMMC_B_CLK0_DIV 66
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#define CLKID_SD_EMMC_C_CLK0_SEL 67
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#define CLKID_SD_EMMC_C_CLK0_DIV 68
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#define CLKID_MPLL0_DIV 69
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#define CLKID_MPLL1_DIV 70
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#define CLKID_MPLL2_DIV 71
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#define CLKID_MPLL3_DIV 72
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#define CLKID_MPLL_PREDIV 73
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#define CLKID_FCLK_DIV2_DIV 75
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#define CLKID_FCLK_DIV3_DIV 76
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#define CLKID_FCLK_DIV4_DIV 77
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#define CLKID_FCLK_DIV5_DIV 78
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#define CLKID_FCLK_DIV7_DIV 79
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#define CLKID_FCLK_DIV2P5_DIV 100
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#define CLKID_FIXED_PLL_DCO 101
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#define CLKID_SYS_PLL_DCO 102
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#define CLKID_GP0_PLL_DCO 103
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#define CLKID_HIFI_PLL_DCO 104
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#define CLKID_VPU_0_DIV 111
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#define CLKID_VPU_1_DIV 114
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#define CLKID_VAPB_0_DIV 118
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#define CLKID_VAPB_1_DIV 121
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#define CLKID_HDMI_PLL_DCO 125
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#define CLKID_HDMI_PLL_OD 126
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#define CLKID_HDMI_PLL_OD2 127
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#define CLKID_VID_PLL_SEL 130
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#define CLKID_VID_PLL_DIV 131
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#define CLKID_VCLK_SEL 132
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#define CLKID_VCLK2_SEL 133
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#define CLKID_VCLK_INPUT 134
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#define CLKID_VCLK2_INPUT 135
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#define CLKID_VCLK_DIV 136
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#define CLKID_VCLK2_DIV 137
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#define CLKID_VCLK_DIV2_EN 140
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#define CLKID_VCLK_DIV4_EN 141
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#define CLKID_VCLK_DIV6_EN 142
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#define CLKID_VCLK_DIV12_EN 143
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#define CLKID_VCLK2_DIV2_EN 144
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#define CLKID_VCLK2_DIV4_EN 145
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#define CLKID_VCLK2_DIV6_EN 146
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#define CLKID_VCLK2_DIV12_EN 147
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#define CLKID_CTS_ENCI_SEL 158
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#define CLKID_CTS_ENCP_SEL 159
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#define CLKID_CTS_VDAC_SEL 160
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#define CLKID_HDMI_TX_SEL 161
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#define CLKID_HDMI_SEL 166
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#define CLKID_HDMI_DIV 167
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#define CLKID_MALI_0_DIV 170
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#define CLKID_MALI_1_DIV 173
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#define CLKID_MPLL_50M_DIV 176
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#define CLKID_SYS_PLL_DIV16_EN 178
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#define CLKID_SYS_PLL_DIV16 179
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#define CLKID_CPU_CLK_DYN0_SEL 180
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#define CLKID_CPU_CLK_DYN0_DIV 181
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#define CLKID_CPU_CLK_DYN0 182
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#define CLKID_CPU_CLK_DYN1_SEL 183
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#define CLKID_CPU_CLK_DYN1_DIV 184
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#define CLKID_CPU_CLK_DYN1 185
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#define CLKID_CPU_CLK_DYN 186
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#define CLKID_CPU_CLK_DIV16_EN 188
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#define CLKID_CPU_CLK_DIV16 189
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#define CLKID_CPU_CLK_APB_DIV 190
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#define CLKID_CPU_CLK_APB 191
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#define CLKID_CPU_CLK_ATB_DIV 192
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#define CLKID_CPU_CLK_ATB 193
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#define CLKID_CPU_CLK_AXI_DIV 194
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#define CLKID_CPU_CLK_AXI 195
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#define CLKID_CPU_CLK_TRACE_DIV 196
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#define CLKID_CPU_CLK_TRACE 197
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#define CLKID_PCIE_PLL_DCO 198
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#define CLKID_PCIE_PLL_DCO_DIV2 199
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#define CLKID_PCIE_PLL_OD 200
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#define CLKID_VDEC_1_SEL 202
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#define CLKID_VDEC_1_DIV 203
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#define CLKID_VDEC_HEVC_SEL 205
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#define CLKID_VDEC_HEVC_DIV 206
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#define CLKID_VDEC_HEVCF_SEL 208
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#define CLKID_VDEC_HEVCF_DIV 209
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#define CLKID_TS_DIV 211
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#define CLKID_SYS1_PLL_DCO 213
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#define CLKID_SYS1_PLL 214
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#define CLKID_SYS1_PLL_DIV16_EN 215
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#define CLKID_SYS1_PLL_DIV16 216
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#define CLKID_CPUB_CLK_DYN0_SEL 217
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#define CLKID_CPUB_CLK_DYN0_DIV 218
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#define CLKID_CPUB_CLK_DYN0 219
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#define CLKID_CPUB_CLK_DYN1_SEL 220
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#define CLKID_CPUB_CLK_DYN1_DIV 221
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#define CLKID_CPUB_CLK_DYN1 222
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#define CLKID_CPUB_CLK_DYN 223
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#define CLKID_CPUB_CLK_DIV16_EN 225
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#define CLKID_CPUB_CLK_DIV16 226
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#define CLKID_CPUB_CLK_DIV2 227
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#define CLKID_CPUB_CLK_DIV3 228
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#define CLKID_CPUB_CLK_DIV4 229
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#define CLKID_CPUB_CLK_DIV5 230
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#define CLKID_CPUB_CLK_DIV6 231
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#define CLKID_CPUB_CLK_DIV7 232
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#define CLKID_CPUB_CLK_DIV8 233
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#define CLKID_CPUB_CLK_APB_SEL 234
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#define CLKID_CPUB_CLK_APB 235
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#define CLKID_CPUB_CLK_ATB_SEL 236
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#define CLKID_CPUB_CLK_ATB 237
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#define CLKID_CPUB_CLK_AXI_SEL 238
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#define CLKID_CPUB_CLK_AXI 239
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#define CLKID_CPUB_CLK_TRACE_SEL 240
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#define CLKID_CPUB_CLK_TRACE 241
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#define CLKID_GP1_PLL_DCO 242
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#define CLKID_DSU_CLK_DYN0_SEL 244
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#define CLKID_DSU_CLK_DYN0_DIV 245
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#define CLKID_DSU_CLK_DYN0 246
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#define CLKID_DSU_CLK_DYN1_SEL 247
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#define CLKID_DSU_CLK_DYN1_DIV 248
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#define CLKID_DSU_CLK_DYN1 249
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#define CLKID_DSU_CLK_DYN 250
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#define CLKID_DSU_CLK_FINAL 251
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#define NR_CLKS 256
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/g12a-clkc.h>
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#endif /* __G12A_H */
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