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Using the PLL in master mode requires using an external connection between one of the GPIO pins (configured as PLL/4 output) and the SCK pin. It also requires the external clock to be fed to some other GPIO pin instead of the SCK pin. This is described for the PCM5122 chip in the answers to the forum post "PCM5122 DAC as I2S master troubles with PLL mode" at the TI E2E community pages (1). The clocking functionality is also much better described in the datasheet for the chip PCM5242, which seems to be register compatible with PCM512x and PCM514x (which both have severely lacking datasheets). (1) http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/267830 Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Mark Brown <broonie@kernel.org>
53 lines
1.4 KiB
Plaintext
53 lines
1.4 KiB
Plaintext
PCM512x audio CODECs
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These devices support both I2C and SPI (configured with pin strapping
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on the board).
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Required properties:
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- compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or
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"ti,pcm5142"
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- reg : the I2C address of the device for I2C, the chip select
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number for SPI.
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- AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the
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device, as covered in bindings/regulator/regulator.txt
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Optional properties:
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- clocks : A clock specifier for the clock connected as SCLK. If this
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is absent the device will be configured to clock from BCLK. If pll-in
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and pll-out are specified in addition to a clock, the device is
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configured to accept clock input on a specified gpio pin.
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- pll-in, pll-out : gpio pins used to connect the pll using <1>
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through <6>. The device will be configured for clock input on the
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given pll-in pin and PLL output on the given pll-out pin. An
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external connection from the pll-out pin to the SCLK pin is assumed.
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Examples:
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pcm5122: pcm5122@4c {
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compatible = "ti,pcm5122";
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reg = <0x4c>;
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AVDD-supply = <®_3v3_analog>;
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DVDD-supply = <®_1v8>;
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CPVDD-supply = <®_3v3>;
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};
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pcm5142: pcm5142@4c {
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compatible = "ti,pcm5142";
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reg = <0x4c>;
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AVDD-supply = <®_3v3_analog>;
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DVDD-supply = <®_1v8>;
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CPVDD-supply = <®_3v3>;
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clocks = <&sck>;
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pll-in = <3>;
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pll-out = <6>;
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};
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