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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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78cdbbdac0
The DSP instance creation also loads the firmware on DSPs. For library load the firmware names come from topology so can't be loaded at object creation. So split the firmware load and object creation. FW load is now called after topology init in platform probe. Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
129 lines
3.6 KiB
C
129 lines
3.6 KiB
C
/*
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* skl.h - HD Audio skylake defintions.
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*
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* Copyright (C) 2015 Intel Corp
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* Author: Jeeja KP <jeeja.kp@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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*/
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#ifndef __SOUND_SOC_SKL_H
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#define __SOUND_SOC_SKL_H
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#include <sound/hda_register.h>
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#include <sound/hdaudio_ext.h>
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#include "skl-nhlt.h"
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#define SKL_SUSPEND_DELAY 2000
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/* Vendor Specific Registers */
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#define AZX_REG_VS_EM1 0x1000
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#define AZX_REG_VS_INRC 0x1004
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#define AZX_REG_VS_OUTRC 0x1008
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#define AZX_REG_VS_FIFOTRK 0x100C
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#define AZX_REG_VS_FIFOTRK2 0x1010
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#define AZX_REG_VS_EM2 0x1030
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#define AZX_REG_VS_EM3L 0x1038
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#define AZX_REG_VS_EM3U 0x103C
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#define AZX_REG_VS_EM4L 0x1040
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#define AZX_REG_VS_EM4U 0x1044
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#define AZX_REG_VS_LTRC 0x1048
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#define AZX_REG_VS_D0I3C 0x104A
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#define AZX_REG_VS_PCE 0x104B
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#define AZX_REG_VS_L2MAGC 0x1050
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#define AZX_REG_VS_L2LAHPT 0x1054
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#define AZX_REG_VS_SDXDPIB_XBASE 0x1084
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#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
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#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
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#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
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#define AZX_PCIREG_PGCTL 0x44
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#define AZX_PGCTL_LSRMD_MASK (1 << 4)
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#define AZX_PCIREG_CGCTL 0x48
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#define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
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struct skl_dsp_resource {
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u32 max_mcps;
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u32 max_mem;
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u32 mcps;
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u32 mem;
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};
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struct skl {
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struct hdac_ext_bus ebus;
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struct pci_dev *pci;
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unsigned int init_failed:1; /* delayed init failed */
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struct platform_device *dmic_dev;
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struct platform_device *i2s_dev;
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struct snd_soc_platform *platform;
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struct nhlt_acpi_table *nhlt; /* nhlt ptr */
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struct skl_sst *skl_sst; /* sst skl ctx */
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struct skl_dsp_resource resource;
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struct list_head ppl_list;
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const char *fw_name;
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char tplg_name[64];
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unsigned short pci_id;
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const struct firmware *tplg;
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int supend_active;
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};
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#define skl_to_ebus(s) (&(s)->ebus)
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#define ebus_to_skl(sbus) \
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container_of(sbus, struct skl, sbus)
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/* to pass dai dma data */
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struct skl_dma_params {
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u32 format;
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u8 stream_tag;
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};
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/* to pass dmic data */
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struct skl_machine_pdata {
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u32 dmic_num;
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};
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struct skl_dsp_ops {
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int id;
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struct skl_dsp_loader_ops (*loader_ops)(void);
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int (*init)(struct device *dev, void __iomem *mmio_base,
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int irq, const char *fw_name,
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struct skl_dsp_loader_ops loader_ops,
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struct skl_sst **skl_sst);
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int (*init_fw)(struct device *dev, struct skl_sst *ctx);
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void (*cleanup)(struct device *dev, struct skl_sst *ctx);
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};
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int skl_platform_unregister(struct device *dev);
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int skl_platform_register(struct device *dev);
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struct nhlt_acpi_table *skl_nhlt_init(struct device *dev);
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void skl_nhlt_free(struct nhlt_acpi_table *addr);
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struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
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u8 link_type, u8 s_fmt, u8 no_ch, u32 s_rate, u8 dirn);
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int skl_get_dmic_geo(struct skl *skl);
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int skl_nhlt_update_topology_bin(struct skl *skl);
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int skl_init_dsp(struct skl *skl);
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int skl_free_dsp(struct skl *skl);
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int skl_suspend_dsp(struct skl *skl);
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int skl_resume_dsp(struct skl *skl);
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void skl_cleanup_resources(struct skl *skl);
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const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
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#endif /* __SOUND_SOC_SKL_H */
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