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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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732f2ab7af
Use the phylib support in the kernel to communicate with and control an MDIO attached PHY. Use the hardware's MDIO communication mechanism to communicate with the PHY. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2705 lines
73 KiB
C
2705 lines
73 KiB
C
/*
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* AMD 10Gb Ethernet driver
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*
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* This file is available to you under your choice of the following two
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* licenses:
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*
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* License 1: GPLv2
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*
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* Copyright (c) 2016 Advanced Micro Devices, Inc.
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*
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* This file is free software; you may copy, redistribute and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or (at
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* your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
|
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* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
|
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* annotated with this license and the Software, to deal in the Software
|
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* without restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
|
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* of the Software, and to permit persons to whom the Software is furnished
|
|
* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
|
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* License 2: Modified BSD
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*
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* Copyright (c) 2016 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
|
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* This file incorporates work covered by the following copyright and
|
|
* permission notice:
|
|
* The Synopsys DWC ETHER XGMAC Software Driver and documentation
|
|
* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
|
|
* Inc. unless otherwise expressly agreed to in writing between Synopsys
|
|
* and you.
|
|
*
|
|
* The Software IS NOT an item of Licensed Software or Licensed Product
|
|
* under any End User Software License Agreement or Agreement for Licensed
|
|
* Product with Synopsys or any supplement thereto. Permission is hereby
|
|
* granted, free of charge, to any person obtaining a copy of this software
|
|
* annotated with this license and the Software, to deal in the Software
|
|
* without restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
|
|
* of the Software, and to permit persons to whom the Software is furnished
|
|
* to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included
|
|
* in all copies or substantial portions of the Software.
|
|
*
|
|
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
|
|
* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
|
* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
|
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/kmod.h>
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#include <linux/mdio.h>
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#include <linux/phy.h>
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#include "xgbe.h"
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#include "xgbe-common.h"
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#define XGBE_PHY_PORT_SPEED_100 BIT(0)
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#define XGBE_PHY_PORT_SPEED_1000 BIT(1)
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#define XGBE_PHY_PORT_SPEED_2500 BIT(2)
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#define XGBE_PHY_PORT_SPEED_10000 BIT(3)
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#define XGBE_MUTEX_RELEASE 0x80000000
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#define XGBE_SFP_DIRECT 7
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/* I2C target addresses */
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#define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
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#define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
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#define XGBE_SFP_PHY_ADDRESS 0x56
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#define XGBE_GPIO_ADDRESS_PCA9555 0x20
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/* SFP sideband signal indicators */
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#define XGBE_GPIO_NO_TX_FAULT BIT(0)
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#define XGBE_GPIO_NO_RATE_SELECT BIT(1)
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#define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
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#define XGBE_GPIO_NO_RX_LOS BIT(3)
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/* Rate-change complete wait/retry count */
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#define XGBE_RATECHANGE_COUNT 500
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enum xgbe_port_mode {
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XGBE_PORT_MODE_RSVD = 0,
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XGBE_PORT_MODE_BACKPLANE,
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XGBE_PORT_MODE_BACKPLANE_2500,
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XGBE_PORT_MODE_1000BASE_T,
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XGBE_PORT_MODE_1000BASE_X,
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XGBE_PORT_MODE_NBASE_T,
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XGBE_PORT_MODE_10GBASE_T,
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XGBE_PORT_MODE_10GBASE_R,
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XGBE_PORT_MODE_SFP,
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XGBE_PORT_MODE_MAX,
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};
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enum xgbe_conn_type {
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XGBE_CONN_TYPE_NONE = 0,
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XGBE_CONN_TYPE_SFP,
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XGBE_CONN_TYPE_MDIO,
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XGBE_CONN_TYPE_BACKPLANE,
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XGBE_CONN_TYPE_MAX,
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};
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/* SFP/SFP+ related definitions */
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enum xgbe_sfp_comm {
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XGBE_SFP_COMM_DIRECT = 0,
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XGBE_SFP_COMM_PCA9545,
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};
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enum xgbe_sfp_cable {
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XGBE_SFP_CABLE_UNKNOWN = 0,
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XGBE_SFP_CABLE_ACTIVE,
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XGBE_SFP_CABLE_PASSIVE,
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};
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enum xgbe_sfp_base {
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XGBE_SFP_BASE_UNKNOWN = 0,
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XGBE_SFP_BASE_1000_T,
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XGBE_SFP_BASE_1000_SX,
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XGBE_SFP_BASE_1000_LX,
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XGBE_SFP_BASE_1000_CX,
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XGBE_SFP_BASE_10000_SR,
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XGBE_SFP_BASE_10000_LR,
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XGBE_SFP_BASE_10000_LRM,
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XGBE_SFP_BASE_10000_ER,
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XGBE_SFP_BASE_10000_CR,
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};
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enum xgbe_sfp_speed {
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XGBE_SFP_SPEED_UNKNOWN = 0,
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XGBE_SFP_SPEED_100_1000,
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XGBE_SFP_SPEED_1000,
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XGBE_SFP_SPEED_10000,
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};
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/* SFP Serial ID Base ID values relative to an offset of 0 */
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#define XGBE_SFP_BASE_ID 0
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#define XGBE_SFP_ID_SFP 0x03
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#define XGBE_SFP_BASE_EXT_ID 1
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#define XGBE_SFP_EXT_ID_SFP 0x04
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#define XGBE_SFP_BASE_10GBE_CC 3
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#define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
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#define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
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#define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
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#define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
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#define XGBE_SFP_BASE_1GBE_CC 6
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#define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
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#define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
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#define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
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#define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
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#define XGBE_SFP_BASE_CABLE 8
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#define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
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#define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
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#define XGBE_SFP_BASE_BR 12
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#define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
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#define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
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#define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
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#define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
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#define XGBE_SFP_BASE_CU_CABLE_LEN 18
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#define XGBE_SFP_BASE_VENDOR_NAME 20
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#define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
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#define XGBE_SFP_BASE_VENDOR_PN 40
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#define XGBE_SFP_BASE_VENDOR_PN_LEN 16
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#define XGBE_SFP_BASE_VENDOR_REV 56
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#define XGBE_SFP_BASE_VENDOR_REV_LEN 4
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#define XGBE_SFP_BASE_CC 63
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/* SFP Serial ID Extended ID values relative to an offset of 64 */
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#define XGBE_SFP_BASE_VENDOR_SN 4
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#define XGBE_SFP_BASE_VENDOR_SN_LEN 16
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#define XGBE_SFP_EXTD_DIAG 28
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#define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
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#define XGBE_SFP_EXTD_SFF_8472 30
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#define XGBE_SFP_EXTD_CC 31
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struct xgbe_sfp_eeprom {
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u8 base[64];
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u8 extd[32];
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u8 vendor[32];
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};
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#define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
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#define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
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struct xgbe_sfp_ascii {
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union {
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char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
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char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
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char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
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char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
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} u;
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};
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/* MDIO PHY reset types */
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enum xgbe_mdio_reset {
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XGBE_MDIO_RESET_NONE = 0,
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XGBE_MDIO_RESET_I2C_GPIO,
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XGBE_MDIO_RESET_INT_GPIO,
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XGBE_MDIO_RESET_MAX,
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};
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/* PHY related configuration information */
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struct xgbe_phy_data {
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enum xgbe_port_mode port_mode;
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unsigned int port_id;
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unsigned int port_speeds;
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enum xgbe_conn_type conn_type;
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enum xgbe_mode cur_mode;
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enum xgbe_mode start_mode;
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unsigned int rrc_count;
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unsigned int mdio_addr;
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unsigned int comm_owned;
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/* SFP Support */
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enum xgbe_sfp_comm sfp_comm;
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unsigned int sfp_mux_address;
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unsigned int sfp_mux_channel;
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unsigned int sfp_gpio_address;
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unsigned int sfp_gpio_mask;
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unsigned int sfp_gpio_rx_los;
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unsigned int sfp_gpio_tx_fault;
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unsigned int sfp_gpio_mod_absent;
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unsigned int sfp_gpio_rate_select;
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unsigned int sfp_rx_los;
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unsigned int sfp_tx_fault;
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unsigned int sfp_mod_absent;
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unsigned int sfp_diags;
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unsigned int sfp_changed;
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unsigned int sfp_phy_avail;
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unsigned int sfp_cable_len;
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enum xgbe_sfp_base sfp_base;
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enum xgbe_sfp_cable sfp_cable;
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enum xgbe_sfp_speed sfp_speed;
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struct xgbe_sfp_eeprom sfp_eeprom;
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/* External PHY support */
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enum xgbe_mdio_mode phydev_mode;
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struct mii_bus *mii;
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struct phy_device *phydev;
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enum xgbe_mdio_reset mdio_reset;
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unsigned int mdio_reset_addr;
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unsigned int mdio_reset_gpio;
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};
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/* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
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static DEFINE_MUTEX(xgbe_phy_comm_lock);
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static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
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static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
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struct xgbe_i2c_op *i2c_op)
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{
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struct xgbe_phy_data *phy_data = pdata->phy_data;
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|
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/* Be sure we own the bus */
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if (WARN_ON(!phy_data->comm_owned))
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return -EIO;
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|
|
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return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
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}
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|
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static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
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void *val, unsigned int val_len)
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{
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struct xgbe_i2c_op i2c_op;
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int retry, ret;
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retry = 1;
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again:
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/* Write the specfied register */
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i2c_op.cmd = XGBE_I2C_CMD_WRITE;
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i2c_op.target = target;
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i2c_op.len = val_len;
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i2c_op.buf = val;
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ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
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if ((ret == -EAGAIN) && retry--)
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goto again;
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|
|
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return ret;
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|
}
|
|
|
|
static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
|
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void *reg, unsigned int reg_len,
|
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void *val, unsigned int val_len)
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{
|
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struct xgbe_i2c_op i2c_op;
|
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int retry, ret;
|
|
|
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retry = 1;
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again1:
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/* Set the specified register to read */
|
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i2c_op.cmd = XGBE_I2C_CMD_WRITE;
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i2c_op.target = target;
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i2c_op.len = reg_len;
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i2c_op.buf = reg;
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ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
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if (ret) {
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if ((ret == -EAGAIN) && retry--)
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goto again1;
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|
|
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return ret;
|
|
}
|
|
|
|
retry = 1;
|
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again2:
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/* Read the specfied register */
|
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i2c_op.cmd = XGBE_I2C_CMD_READ;
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i2c_op.target = target;
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i2c_op.len = val_len;
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i2c_op.buf = val;
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ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
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if ((ret == -EAGAIN) && retry--)
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goto again2;
|
|
|
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return ret;
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|
}
|
|
|
|
static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
|
|
{
|
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struct xgbe_phy_data *phy_data = pdata->phy_data;
|
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struct xgbe_i2c_op i2c_op;
|
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u8 mux_channel;
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|
|
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if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
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return 0;
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|
|
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/* Select no mux channels */
|
|
mux_channel = 0;
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i2c_op.cmd = XGBE_I2C_CMD_WRITE;
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i2c_op.target = phy_data->sfp_mux_address;
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i2c_op.len = sizeof(mux_channel);
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i2c_op.buf = &mux_channel;
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|
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return xgbe_phy_i2c_xfer(pdata, &i2c_op);
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}
|
|
|
|
static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
|
|
{
|
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struct xgbe_phy_data *phy_data = pdata->phy_data;
|
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struct xgbe_i2c_op i2c_op;
|
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u8 mux_channel;
|
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|
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if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
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return 0;
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|
|
/* Select desired mux channel */
|
|
mux_channel = 1 << phy_data->sfp_mux_channel;
|
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i2c_op.cmd = XGBE_I2C_CMD_WRITE;
|
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i2c_op.target = phy_data->sfp_mux_address;
|
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i2c_op.len = sizeof(mux_channel);
|
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i2c_op.buf = &mux_channel;
|
|
|
|
return xgbe_phy_i2c_xfer(pdata, &i2c_op);
|
|
}
|
|
|
|
static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
phy_data->comm_owned = 0;
|
|
|
|
mutex_unlock(&xgbe_phy_comm_lock);
|
|
}
|
|
|
|
static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned long timeout;
|
|
unsigned int mutex_id;
|
|
|
|
if (phy_data->comm_owned)
|
|
return 0;
|
|
|
|
/* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
|
|
* the driver needs to take the software mutex and then the hardware
|
|
* mutexes before being able to use the busses.
|
|
*/
|
|
mutex_lock(&xgbe_phy_comm_lock);
|
|
|
|
/* Clear the mutexes */
|
|
XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
|
|
XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
|
|
|
|
/* Mutex formats are the same for I2C and MDIO/GPIO */
|
|
mutex_id = 0;
|
|
XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
|
|
XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
|
|
|
|
timeout = jiffies + (5 * HZ);
|
|
while (time_before(jiffies, timeout)) {
|
|
/* Must be all zeroes in order to obtain the mutex */
|
|
if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
|
|
XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
|
|
usleep_range(100, 200);
|
|
continue;
|
|
}
|
|
|
|
/* Obtain the mutex */
|
|
XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
|
|
XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
|
|
|
|
phy_data->comm_owned = 1;
|
|
return 0;
|
|
}
|
|
|
|
mutex_unlock(&xgbe_phy_comm_lock);
|
|
|
|
netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
|
|
int reg, u16 val)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
if (reg & MII_ADDR_C45) {
|
|
if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
|
|
return -ENOTSUPP;
|
|
} else {
|
|
if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
|
|
}
|
|
|
|
static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
|
|
{
|
|
__be16 *mii_val;
|
|
u8 mii_data[3];
|
|
int ret;
|
|
|
|
ret = xgbe_phy_sfp_get_mux(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mii_data[0] = reg & 0xff;
|
|
mii_val = (__be16 *)&mii_data[1];
|
|
*mii_val = cpu_to_be16(val);
|
|
|
|
ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
|
|
mii_data, sizeof(mii_data));
|
|
|
|
xgbe_phy_sfp_put_mux(pdata);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
|
|
{
|
|
struct xgbe_prv_data *pdata = mii->priv;
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
int ret;
|
|
|
|
ret = xgbe_phy_get_comm_ownership(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
|
|
ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
|
|
else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
|
|
ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
|
|
else
|
|
ret = -ENOTSUPP;
|
|
|
|
xgbe_phy_put_comm_ownership(pdata);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
|
|
int reg)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
if (reg & MII_ADDR_C45) {
|
|
if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
|
|
return -ENOTSUPP;
|
|
} else {
|
|
if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
|
|
}
|
|
|
|
static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
|
|
{
|
|
__be16 mii_val;
|
|
u8 mii_reg;
|
|
int ret;
|
|
|
|
ret = xgbe_phy_sfp_get_mux(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mii_reg = reg;
|
|
ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
|
|
&mii_reg, sizeof(mii_reg),
|
|
&mii_val, sizeof(mii_val));
|
|
if (!ret)
|
|
ret = be16_to_cpu(mii_val);
|
|
|
|
xgbe_phy_sfp_put_mux(pdata);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
|
|
{
|
|
struct xgbe_prv_data *pdata = mii->priv;
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
int ret;
|
|
|
|
ret = xgbe_phy_get_comm_ownership(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
|
|
ret = xgbe_phy_i2c_mii_read(pdata, reg);
|
|
else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
|
|
ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
|
|
else
|
|
ret = -ENOTSUPP;
|
|
|
|
xgbe_phy_put_comm_ownership(pdata);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
if (phy_data->sfp_mod_absent) {
|
|
pdata->phy.speed = SPEED_UNKNOWN;
|
|
pdata->phy.duplex = DUPLEX_UNKNOWN;
|
|
pdata->phy.autoneg = AUTONEG_ENABLE;
|
|
pdata->phy.advertising = pdata->phy.supported;
|
|
}
|
|
|
|
pdata->phy.advertising &= ~ADVERTISED_Autoneg;
|
|
pdata->phy.advertising &= ~ADVERTISED_TP;
|
|
pdata->phy.advertising &= ~ADVERTISED_FIBRE;
|
|
pdata->phy.advertising &= ~ADVERTISED_100baseT_Full;
|
|
pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full;
|
|
pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full;
|
|
pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC;
|
|
|
|
switch (phy_data->sfp_base) {
|
|
case XGBE_SFP_BASE_1000_T:
|
|
case XGBE_SFP_BASE_1000_SX:
|
|
case XGBE_SFP_BASE_1000_LX:
|
|
case XGBE_SFP_BASE_1000_CX:
|
|
pdata->phy.speed = SPEED_UNKNOWN;
|
|
pdata->phy.duplex = DUPLEX_UNKNOWN;
|
|
pdata->phy.autoneg = AUTONEG_ENABLE;
|
|
pdata->phy.advertising |= ADVERTISED_Autoneg;
|
|
break;
|
|
case XGBE_SFP_BASE_10000_SR:
|
|
case XGBE_SFP_BASE_10000_LR:
|
|
case XGBE_SFP_BASE_10000_LRM:
|
|
case XGBE_SFP_BASE_10000_ER:
|
|
case XGBE_SFP_BASE_10000_CR:
|
|
default:
|
|
pdata->phy.speed = SPEED_10000;
|
|
pdata->phy.duplex = DUPLEX_FULL;
|
|
pdata->phy.autoneg = AUTONEG_DISABLE;
|
|
break;
|
|
}
|
|
|
|
switch (phy_data->sfp_base) {
|
|
case XGBE_SFP_BASE_1000_T:
|
|
case XGBE_SFP_BASE_1000_CX:
|
|
case XGBE_SFP_BASE_10000_CR:
|
|
pdata->phy.advertising |= ADVERTISED_TP;
|
|
break;
|
|
default:
|
|
pdata->phy.advertising |= ADVERTISED_FIBRE;
|
|
}
|
|
|
|
switch (phy_data->sfp_speed) {
|
|
case XGBE_SFP_SPEED_100_1000:
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
|
|
pdata->phy.advertising |= ADVERTISED_100baseT_Full;
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
|
|
pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
|
|
break;
|
|
case XGBE_SFP_SPEED_1000:
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
|
|
pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
|
|
break;
|
|
case XGBE_SFP_SPEED_10000:
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
|
|
pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
|
|
break;
|
|
default:
|
|
/* Choose the fastest supported speed */
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
|
|
pdata->phy.advertising |= ADVERTISED_10000baseT_Full;
|
|
else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
|
|
pdata->phy.advertising |= ADVERTISED_1000baseT_Full;
|
|
else if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
|
|
pdata->phy.advertising |= ADVERTISED_100baseT_Full;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
|
|
enum xgbe_sfp_speed sfp_speed)
|
|
{
|
|
u8 *sfp_base, min, max;
|
|
|
|
sfp_base = sfp_eeprom->base;
|
|
|
|
switch (sfp_speed) {
|
|
case XGBE_SFP_SPEED_1000:
|
|
min = XGBE_SFP_BASE_BR_1GBE_MIN;
|
|
max = XGBE_SFP_BASE_BR_1GBE_MAX;
|
|
break;
|
|
case XGBE_SFP_SPEED_10000:
|
|
min = XGBE_SFP_BASE_BR_10GBE_MIN;
|
|
max = XGBE_SFP_BASE_BR_10GBE_MAX;
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
|
|
(sfp_base[XGBE_SFP_BASE_BR] <= max));
|
|
}
|
|
|
|
static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
if (phy_data->phydev) {
|
|
phy_detach(phy_data->phydev);
|
|
phy_device_remove(phy_data->phydev);
|
|
phy_device_free(phy_data->phydev);
|
|
phy_data->phydev = NULL;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int phy_id = phy_data->phydev->phy_id;
|
|
|
|
if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
|
|
return false;
|
|
|
|
/* Enable Base-T AN */
|
|
phy_write(phy_data->phydev, 0x16, 0x0001);
|
|
phy_write(phy_data->phydev, 0x00, 0x9140);
|
|
phy_write(phy_data->phydev, 0x16, 0x0000);
|
|
|
|
/* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
|
|
phy_write(phy_data->phydev, 0x1b, 0x9084);
|
|
phy_write(phy_data->phydev, 0x09, 0x0e00);
|
|
phy_write(phy_data->phydev, 0x00, 0x8140);
|
|
phy_write(phy_data->phydev, 0x04, 0x0d01);
|
|
phy_write(phy_data->phydev, 0x00, 0x9140);
|
|
|
|
phy_data->phydev->supported = PHY_GBIT_FEATURES;
|
|
phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
phy_data->phydev->advertising = phy_data->phydev->supported;
|
|
|
|
netif_dbg(pdata, drv, pdata->netdev,
|
|
"Finisar PHY quirk in place\n");
|
|
|
|
return true;
|
|
}
|
|
|
|
static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
|
|
{
|
|
if (xgbe_phy_finisar_phy_quirks(pdata))
|
|
return;
|
|
}
|
|
|
|
static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
struct phy_device *phydev;
|
|
int ret;
|
|
|
|
/* If we already have a PHY, just return */
|
|
if (phy_data->phydev)
|
|
return 0;
|
|
|
|
/* Check for the use of an external PHY */
|
|
if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
|
|
return 0;
|
|
|
|
/* For SFP, only use an external PHY if available */
|
|
if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
|
|
!phy_data->sfp_phy_avail)
|
|
return 0;
|
|
|
|
/* Create and connect to the PHY device */
|
|
phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
|
|
(phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
|
|
if (IS_ERR(phydev)) {
|
|
netdev_err(pdata->netdev, "get_phy_device failed\n");
|
|
return -ENODEV;
|
|
}
|
|
netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
|
|
phydev->phy_id);
|
|
|
|
/*TODO: If c45, add request_module based on one of the MMD ids? */
|
|
|
|
ret = phy_device_register(phydev);
|
|
if (ret) {
|
|
netdev_err(pdata->netdev, "phy_device_register failed\n");
|
|
phy_device_free(phydev);
|
|
return ret;
|
|
}
|
|
|
|
ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
|
|
PHY_INTERFACE_MODE_SGMII);
|
|
if (ret) {
|
|
netdev_err(pdata->netdev, "phy_attach_direct failed\n");
|
|
phy_device_remove(phydev);
|
|
phy_device_free(phydev);
|
|
return ret;
|
|
}
|
|
phy_data->phydev = phydev;
|
|
|
|
xgbe_phy_external_phy_quirks(pdata);
|
|
phydev->advertising &= pdata->phy.advertising;
|
|
|
|
phy_start_aneg(phy_data->phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
int ret;
|
|
|
|
if (!phy_data->sfp_changed)
|
|
return;
|
|
|
|
phy_data->sfp_phy_avail = 0;
|
|
|
|
if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
|
|
return;
|
|
|
|
/* Check access to the PHY by reading CTRL1 */
|
|
ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
|
|
if (ret < 0)
|
|
return;
|
|
|
|
/* Successfully accessed the PHY */
|
|
phy_data->sfp_phy_avail = 1;
|
|
}
|
|
|
|
static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
|
|
|
|
if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
|
|
XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
|
|
return false;
|
|
|
|
if (!memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
|
|
XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) {
|
|
phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
|
|
phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
|
|
phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
|
|
if (phy_data->sfp_changed)
|
|
netif_dbg(pdata, drv, pdata->netdev,
|
|
"Bel-Fuse SFP quirk in place\n");
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool xgbe_phy_sfp_parse_quirks(struct xgbe_prv_data *pdata)
|
|
{
|
|
if (xgbe_phy_belfuse_parse_quirks(pdata))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
|
|
u8 *sfp_base;
|
|
|
|
sfp_base = sfp_eeprom->base;
|
|
|
|
if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
|
|
return;
|
|
|
|
if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
|
|
return;
|
|
|
|
if (xgbe_phy_sfp_parse_quirks(pdata))
|
|
return;
|
|
|
|
/* Assume ACTIVE cable unless told it is PASSIVE */
|
|
if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
|
|
phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
|
|
phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
|
|
} else {
|
|
phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
|
|
}
|
|
|
|
/* Determine the type of SFP */
|
|
if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
|
|
phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
|
|
else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
|
|
phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
|
|
else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
|
|
phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
|
|
else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
|
|
phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
|
|
else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
|
|
phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
|
|
else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
|
|
phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
|
|
else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
|
|
phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
|
|
else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
|
|
phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
|
|
else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
|
|
xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
|
|
phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
|
|
|
|
switch (phy_data->sfp_base) {
|
|
case XGBE_SFP_BASE_1000_T:
|
|
phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
|
|
break;
|
|
case XGBE_SFP_BASE_1000_SX:
|
|
case XGBE_SFP_BASE_1000_LX:
|
|
case XGBE_SFP_BASE_1000_CX:
|
|
phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
|
|
break;
|
|
case XGBE_SFP_BASE_10000_SR:
|
|
case XGBE_SFP_BASE_10000_LR:
|
|
case XGBE_SFP_BASE_10000_LRM:
|
|
case XGBE_SFP_BASE_10000_ER:
|
|
case XGBE_SFP_BASE_10000_CR:
|
|
phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
|
|
struct xgbe_sfp_eeprom *sfp_eeprom)
|
|
{
|
|
struct xgbe_sfp_ascii sfp_ascii;
|
|
char *sfp_data = (char *)&sfp_ascii;
|
|
|
|
netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
|
|
memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
|
|
XGBE_SFP_BASE_VENDOR_NAME_LEN);
|
|
sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
|
|
netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
|
|
sfp_data);
|
|
|
|
memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
|
|
XGBE_SFP_BASE_VENDOR_PN_LEN);
|
|
sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
|
|
netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
|
|
sfp_data);
|
|
|
|
memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
|
|
XGBE_SFP_BASE_VENDOR_REV_LEN);
|
|
sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
|
|
netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
|
|
sfp_data);
|
|
|
|
memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
|
|
XGBE_SFP_BASE_VENDOR_SN_LEN);
|
|
sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
|
|
netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
|
|
sfp_data);
|
|
}
|
|
|
|
static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
|
|
{
|
|
u8 cc;
|
|
|
|
for (cc = 0; len; buf++, len--)
|
|
cc += *buf;
|
|
|
|
return (cc == cc_in) ? true : false;
|
|
}
|
|
|
|
static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
struct xgbe_sfp_eeprom sfp_eeprom;
|
|
u8 eeprom_addr;
|
|
int ret;
|
|
|
|
ret = xgbe_phy_sfp_get_mux(pdata);
|
|
if (ret) {
|
|
netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Read the SFP serial ID eeprom */
|
|
eeprom_addr = 0;
|
|
ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
|
|
&eeprom_addr, sizeof(eeprom_addr),
|
|
&sfp_eeprom, sizeof(sfp_eeprom));
|
|
if (ret) {
|
|
netdev_err(pdata->netdev, "I2C error reading SFP EEPROM\n");
|
|
goto put;
|
|
}
|
|
|
|
/* Validate the contents read */
|
|
if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
|
|
sfp_eeprom.base,
|
|
sizeof(sfp_eeprom.base) - 1)) {
|
|
ret = -EINVAL;
|
|
goto put;
|
|
}
|
|
|
|
if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
|
|
sfp_eeprom.extd,
|
|
sizeof(sfp_eeprom.extd) - 1)) {
|
|
ret = -EINVAL;
|
|
goto put;
|
|
}
|
|
|
|
/* Check for an added or changed SFP */
|
|
if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
|
|
phy_data->sfp_changed = 1;
|
|
|
|
if (netif_msg_drv(pdata))
|
|
xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
|
|
|
|
memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
|
|
|
|
if (sfp_eeprom.extd[XGBE_SFP_EXTD_SFF_8472]) {
|
|
u8 diag_type = sfp_eeprom.extd[XGBE_SFP_EXTD_DIAG];
|
|
|
|
if (!(diag_type & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
|
|
phy_data->sfp_diags = 1;
|
|
}
|
|
|
|
xgbe_phy_free_phy_device(pdata);
|
|
} else {
|
|
phy_data->sfp_changed = 0;
|
|
}
|
|
|
|
put:
|
|
xgbe_phy_sfp_put_mux(pdata);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int gpio_input;
|
|
u8 gpio_reg, gpio_ports[2];
|
|
int ret;
|
|
|
|
/* Read the input port registers */
|
|
gpio_reg = 0;
|
|
ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
|
|
&gpio_reg, sizeof(gpio_reg),
|
|
gpio_ports, sizeof(gpio_ports));
|
|
if (ret) {
|
|
netdev_err(pdata->netdev, "I2C error reading SFP GPIOs\n");
|
|
return;
|
|
}
|
|
|
|
gpio_input = (gpio_ports[1] << 8) | gpio_ports[0];
|
|
|
|
if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) {
|
|
/* No GPIO, just assume the module is present for now */
|
|
phy_data->sfp_mod_absent = 0;
|
|
} else {
|
|
if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent)))
|
|
phy_data->sfp_mod_absent = 0;
|
|
}
|
|
|
|
if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) &&
|
|
(gpio_input & (1 << phy_data->sfp_gpio_rx_los)))
|
|
phy_data->sfp_rx_los = 1;
|
|
|
|
if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) &&
|
|
(gpio_input & (1 << phy_data->sfp_gpio_tx_fault)))
|
|
phy_data->sfp_tx_fault = 1;
|
|
}
|
|
|
|
static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
xgbe_phy_free_phy_device(pdata);
|
|
|
|
phy_data->sfp_mod_absent = 1;
|
|
phy_data->sfp_phy_avail = 0;
|
|
memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
|
|
}
|
|
|
|
static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
|
|
{
|
|
phy_data->sfp_rx_los = 0;
|
|
phy_data->sfp_tx_fault = 0;
|
|
phy_data->sfp_mod_absent = 1;
|
|
phy_data->sfp_diags = 0;
|
|
phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
|
|
phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
|
|
phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
|
|
}
|
|
|
|
static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
int ret;
|
|
|
|
/* Reset the SFP signals and info */
|
|
xgbe_phy_sfp_reset(phy_data);
|
|
|
|
ret = xgbe_phy_get_comm_ownership(pdata);
|
|
if (ret)
|
|
return;
|
|
|
|
/* Read the SFP signals and check for module presence */
|
|
xgbe_phy_sfp_signals(pdata);
|
|
if (phy_data->sfp_mod_absent) {
|
|
xgbe_phy_sfp_mod_absent(pdata);
|
|
goto put;
|
|
}
|
|
|
|
ret = xgbe_phy_sfp_read_eeprom(pdata);
|
|
if (ret) {
|
|
/* Treat any error as if there isn't an SFP plugged in */
|
|
xgbe_phy_sfp_reset(phy_data);
|
|
xgbe_phy_sfp_mod_absent(pdata);
|
|
goto put;
|
|
}
|
|
|
|
xgbe_phy_sfp_parse_eeprom(pdata);
|
|
|
|
xgbe_phy_sfp_external_phy(pdata);
|
|
|
|
put:
|
|
xgbe_phy_sfp_phy_settings(pdata);
|
|
|
|
xgbe_phy_put_comm_ownership(pdata);
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
enum xgbe_mode mode;
|
|
|
|
pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
|
|
pdata->phy.lp_advertising |= ADVERTISED_TP;
|
|
|
|
if (pdata->phy.pause_autoneg && phy_data->phydev) {
|
|
/* Flow control is obtained from the attached PHY */
|
|
u16 lcl_adv = 0, rmt_adv = 0;
|
|
u8 fc;
|
|
|
|
pdata->phy.tx_pause = 0;
|
|
pdata->phy.rx_pause = 0;
|
|
|
|
if (phy_data->phydev->advertising & ADVERTISED_Pause)
|
|
lcl_adv |= ADVERTISE_PAUSE_CAP;
|
|
if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
|
|
lcl_adv |= ADVERTISE_PAUSE_ASYM;
|
|
|
|
if (phy_data->phydev->pause)
|
|
rmt_adv |= LPA_PAUSE_CAP;
|
|
if (phy_data->phydev->asym_pause)
|
|
rmt_adv |= LPA_PAUSE_ASYM;
|
|
|
|
fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
|
|
if (fc & FLOW_CTRL_TX)
|
|
pdata->phy.tx_pause = 1;
|
|
if (fc & FLOW_CTRL_RX)
|
|
pdata->phy.rx_pause = 1;
|
|
}
|
|
|
|
switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
|
|
case XGBE_SGMII_AN_LINK_SPEED_100:
|
|
if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
|
|
pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;
|
|
mode = XGBE_MODE_SGMII_100;
|
|
} else {
|
|
/* Half-duplex not supported */
|
|
pdata->phy.lp_advertising |= ADVERTISED_100baseT_Half;
|
|
mode = XGBE_MODE_UNKNOWN;
|
|
}
|
|
break;
|
|
case XGBE_SGMII_AN_LINK_SPEED_1000:
|
|
if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
|
|
pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
|
|
mode = XGBE_MODE_SGMII_1000;
|
|
} else {
|
|
/* Half-duplex not supported */
|
|
pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half;
|
|
mode = XGBE_MODE_UNKNOWN;
|
|
}
|
|
break;
|
|
default:
|
|
mode = XGBE_MODE_UNKNOWN;
|
|
}
|
|
|
|
return mode;
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
|
|
{
|
|
enum xgbe_mode mode;
|
|
unsigned int ad_reg, lp_reg;
|
|
|
|
pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
|
|
pdata->phy.lp_advertising |= ADVERTISED_FIBRE;
|
|
|
|
/* Compare Advertisement and Link Partner register */
|
|
ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
|
|
lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
|
|
if (lp_reg & 0x100)
|
|
pdata->phy.lp_advertising |= ADVERTISED_Pause;
|
|
if (lp_reg & 0x80)
|
|
pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
|
|
|
|
if (pdata->phy.pause_autoneg) {
|
|
/* Set flow control based on auto-negotiation result */
|
|
pdata->phy.tx_pause = 0;
|
|
pdata->phy.rx_pause = 0;
|
|
|
|
if (ad_reg & lp_reg & 0x100) {
|
|
pdata->phy.tx_pause = 1;
|
|
pdata->phy.rx_pause = 1;
|
|
} else if (ad_reg & lp_reg & 0x80) {
|
|
if (ad_reg & 0x100)
|
|
pdata->phy.rx_pause = 1;
|
|
else if (lp_reg & 0x100)
|
|
pdata->phy.tx_pause = 1;
|
|
}
|
|
}
|
|
|
|
if (lp_reg & 0x40)
|
|
pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Half;
|
|
if (lp_reg & 0x20)
|
|
pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;
|
|
|
|
/* Half duplex is not supported */
|
|
ad_reg &= lp_reg;
|
|
mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
|
|
|
|
return mode;
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
|
|
{
|
|
enum xgbe_mode mode;
|
|
unsigned int ad_reg, lp_reg;
|
|
|
|
pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
|
|
pdata->phy.lp_advertising |= ADVERTISED_Backplane;
|
|
|
|
/* Compare Advertisement and Link Partner register 1 */
|
|
ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
|
|
lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
|
|
if (lp_reg & 0x400)
|
|
pdata->phy.lp_advertising |= ADVERTISED_Pause;
|
|
if (lp_reg & 0x800)
|
|
pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
|
|
|
|
if (pdata->phy.pause_autoneg) {
|
|
/* Set flow control based on auto-negotiation result */
|
|
pdata->phy.tx_pause = 0;
|
|
pdata->phy.rx_pause = 0;
|
|
|
|
if (ad_reg & lp_reg & 0x400) {
|
|
pdata->phy.tx_pause = 1;
|
|
pdata->phy.rx_pause = 1;
|
|
} else if (ad_reg & lp_reg & 0x800) {
|
|
if (ad_reg & 0x400)
|
|
pdata->phy.rx_pause = 1;
|
|
else if (lp_reg & 0x400)
|
|
pdata->phy.tx_pause = 1;
|
|
}
|
|
}
|
|
|
|
/* Compare Advertisement and Link Partner register 2 */
|
|
ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
|
|
lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
|
|
if (lp_reg & 0x80)
|
|
pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
|
|
if (lp_reg & 0x20)
|
|
pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
|
|
|
|
ad_reg &= lp_reg;
|
|
if (ad_reg & 0x80)
|
|
mode = XGBE_MODE_KR;
|
|
else if (ad_reg & 0x20)
|
|
mode = XGBE_MODE_KX_1000;
|
|
else
|
|
mode = XGBE_MODE_UNKNOWN;
|
|
|
|
/* Compare Advertisement and Link Partner register 3 */
|
|
ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
|
|
lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
|
|
if (lp_reg & 0xc000)
|
|
pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
|
|
|
|
return mode;
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
|
|
{
|
|
switch (pdata->an_mode) {
|
|
case XGBE_AN_MODE_CL73:
|
|
return xgbe_phy_an73_outcome(pdata);
|
|
case XGBE_AN_MODE_CL37:
|
|
return xgbe_phy_an37_outcome(pdata);
|
|
case XGBE_AN_MODE_CL37_SGMII:
|
|
return xgbe_phy_an37_sgmii_outcome(pdata);
|
|
default:
|
|
return XGBE_MODE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
int ret;
|
|
|
|
ret = xgbe_phy_find_phy_device(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!phy_data->phydev)
|
|
return 0;
|
|
|
|
phy_data->phydev->autoneg = pdata->phy.autoneg;
|
|
phy_data->phydev->advertising = phy_data->phydev->supported &
|
|
pdata->phy.advertising;
|
|
|
|
if (pdata->phy.autoneg != AUTONEG_ENABLE) {
|
|
phy_data->phydev->speed = pdata->phy.speed;
|
|
phy_data->phydev->duplex = pdata->phy.duplex;
|
|
}
|
|
|
|
ret = phy_start_aneg(phy_data->phydev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
|
|
{
|
|
switch (phy_data->sfp_base) {
|
|
case XGBE_SFP_BASE_1000_T:
|
|
return XGBE_AN_MODE_CL37_SGMII;
|
|
case XGBE_SFP_BASE_1000_SX:
|
|
case XGBE_SFP_BASE_1000_LX:
|
|
case XGBE_SFP_BASE_1000_CX:
|
|
return XGBE_AN_MODE_CL37;
|
|
default:
|
|
return XGBE_AN_MODE_NONE;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
switch (phy_data->port_mode) {
|
|
case XGBE_PORT_MODE_BACKPLANE:
|
|
return XGBE_AN_MODE_CL73;
|
|
case XGBE_PORT_MODE_BACKPLANE_2500:
|
|
return XGBE_AN_MODE_NONE;
|
|
case XGBE_PORT_MODE_1000BASE_T:
|
|
return XGBE_AN_MODE_CL37_SGMII;
|
|
case XGBE_PORT_MODE_1000BASE_X:
|
|
return XGBE_AN_MODE_CL37;
|
|
case XGBE_PORT_MODE_NBASE_T:
|
|
return XGBE_AN_MODE_CL37_SGMII;
|
|
case XGBE_PORT_MODE_10GBASE_T:
|
|
return XGBE_AN_MODE_CL73;
|
|
case XGBE_PORT_MODE_10GBASE_R:
|
|
return XGBE_AN_MODE_NONE;
|
|
case XGBE_PORT_MODE_SFP:
|
|
return xgbe_phy_an_sfp_mode(phy_data);
|
|
default:
|
|
return XGBE_AN_MODE_NONE;
|
|
}
|
|
}
|
|
|
|
static void xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)
|
|
{
|
|
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
|
|
return;
|
|
|
|
/* Log if a previous command did not complete */
|
|
netif_dbg(pdata, link, pdata->netdev,
|
|
"firmware mailbox not ready for command\n");
|
|
}
|
|
|
|
static void xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)
|
|
{
|
|
unsigned int wait;
|
|
|
|
/* Wait for command to complete */
|
|
wait = XGBE_RATECHANGE_COUNT;
|
|
while (wait--) {
|
|
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
|
|
return;
|
|
|
|
usleep_range(1000, 2000);
|
|
}
|
|
|
|
netif_dbg(pdata, link, pdata->netdev,
|
|
"firmware mailbox command did not complete\n");
|
|
}
|
|
|
|
static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
|
|
{
|
|
unsigned int s0;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* Receiver Reset Cycle */
|
|
s0 = 0;
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
|
|
}
|
|
|
|
static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
phy_data->cur_mode = XGBE_MODE_UNKNOWN;
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
|
|
}
|
|
|
|
static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int s0;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* 10G/SFI */
|
|
s0 = 0;
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
|
|
if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
|
|
} else {
|
|
if (phy_data->sfp_cable_len <= 1)
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
|
|
else if (phy_data->sfp_cable_len <= 3)
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
|
|
else if (phy_data->sfp_cable_len <= 5)
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
|
|
else
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
|
|
}
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
phy_data->cur_mode = XGBE_MODE_SFI;
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
|
|
}
|
|
|
|
static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int s0;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* 1G/X */
|
|
s0 = 0;
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
phy_data->cur_mode = XGBE_MODE_X;
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
|
|
}
|
|
|
|
static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int s0;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* 1G/SGMII */
|
|
s0 = 0;
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
phy_data->cur_mode = XGBE_MODE_SGMII_1000;
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
|
|
}
|
|
|
|
static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int s0;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* 1G/SGMII */
|
|
s0 = 0;
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
phy_data->cur_mode = XGBE_MODE_SGMII_100;
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
|
|
}
|
|
|
|
static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int s0;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* 10G/KR */
|
|
s0 = 0;
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4);
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
phy_data->cur_mode = XGBE_MODE_KR;
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
|
|
}
|
|
|
|
static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int s0;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* 2.5G/KX */
|
|
s0 = 0;
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2);
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
phy_data->cur_mode = XGBE_MODE_KX_2500;
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
|
|
}
|
|
|
|
static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int s0;
|
|
|
|
xgbe_phy_start_ratechange(pdata);
|
|
|
|
/* 1G/KX */
|
|
s0 = 0;
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1);
|
|
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
|
|
|
|
/* Call FW to make the change */
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
|
|
XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
|
|
XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
|
|
|
|
xgbe_phy_complete_ratechange(pdata);
|
|
|
|
phy_data->cur_mode = XGBE_MODE_KX_1000;
|
|
|
|
netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
return phy_data->cur_mode;
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
/* No switching if not 10GBase-T */
|
|
if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
|
|
return xgbe_phy_cur_mode(pdata);
|
|
|
|
switch (xgbe_phy_cur_mode(pdata)) {
|
|
case XGBE_MODE_SGMII_100:
|
|
case XGBE_MODE_SGMII_1000:
|
|
return XGBE_MODE_KR;
|
|
case XGBE_MODE_KR:
|
|
default:
|
|
return XGBE_MODE_SGMII_1000;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
return XGBE_MODE_KX_2500;
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
/* If we are in KR switch to KX, and vice-versa */
|
|
switch (xgbe_phy_cur_mode(pdata)) {
|
|
case XGBE_MODE_KX_1000:
|
|
return XGBE_MODE_KR;
|
|
case XGBE_MODE_KR:
|
|
default:
|
|
return XGBE_MODE_KX_1000;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
switch (phy_data->port_mode) {
|
|
case XGBE_PORT_MODE_BACKPLANE:
|
|
return xgbe_phy_switch_bp_mode(pdata);
|
|
case XGBE_PORT_MODE_BACKPLANE_2500:
|
|
return xgbe_phy_switch_bp_2500_mode(pdata);
|
|
case XGBE_PORT_MODE_1000BASE_T:
|
|
case XGBE_PORT_MODE_NBASE_T:
|
|
case XGBE_PORT_MODE_10GBASE_T:
|
|
return xgbe_phy_switch_baset_mode(pdata);
|
|
case XGBE_PORT_MODE_1000BASE_X:
|
|
case XGBE_PORT_MODE_10GBASE_R:
|
|
case XGBE_PORT_MODE_SFP:
|
|
/* No switching, so just return current mode */
|
|
return xgbe_phy_cur_mode(pdata);
|
|
default:
|
|
return XGBE_MODE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
|
|
int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_1000:
|
|
return XGBE_MODE_X;
|
|
case SPEED_10000:
|
|
return XGBE_MODE_KR;
|
|
default:
|
|
return XGBE_MODE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
|
|
int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_100:
|
|
return XGBE_MODE_SGMII_100;
|
|
case SPEED_1000:
|
|
return XGBE_MODE_SGMII_1000;
|
|
case SPEED_10000:
|
|
return XGBE_MODE_KR;
|
|
default:
|
|
return XGBE_MODE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
|
|
int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_100:
|
|
return XGBE_MODE_SGMII_100;
|
|
case SPEED_1000:
|
|
if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
|
|
return XGBE_MODE_SGMII_1000;
|
|
else
|
|
return XGBE_MODE_X;
|
|
case SPEED_10000:
|
|
case SPEED_UNKNOWN:
|
|
return XGBE_MODE_SFI;
|
|
default:
|
|
return XGBE_MODE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_2500:
|
|
return XGBE_MODE_KX_2500;
|
|
default:
|
|
return XGBE_MODE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_1000:
|
|
return XGBE_MODE_KX_1000;
|
|
case SPEED_10000:
|
|
return XGBE_MODE_KR;
|
|
default:
|
|
return XGBE_MODE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
|
|
int speed)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
switch (phy_data->port_mode) {
|
|
case XGBE_PORT_MODE_BACKPLANE:
|
|
return xgbe_phy_get_bp_mode(speed);
|
|
case XGBE_PORT_MODE_BACKPLANE_2500:
|
|
return xgbe_phy_get_bp_2500_mode(speed);
|
|
case XGBE_PORT_MODE_1000BASE_T:
|
|
case XGBE_PORT_MODE_NBASE_T:
|
|
case XGBE_PORT_MODE_10GBASE_T:
|
|
return xgbe_phy_get_baset_mode(phy_data, speed);
|
|
case XGBE_PORT_MODE_1000BASE_X:
|
|
case XGBE_PORT_MODE_10GBASE_R:
|
|
return xgbe_phy_get_basex_mode(phy_data, speed);
|
|
case XGBE_PORT_MODE_SFP:
|
|
return xgbe_phy_get_sfp_mode(phy_data, speed);
|
|
default:
|
|
return XGBE_MODE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
|
|
{
|
|
switch (mode) {
|
|
case XGBE_MODE_KX_1000:
|
|
xgbe_phy_kx_1000_mode(pdata);
|
|
break;
|
|
case XGBE_MODE_KX_2500:
|
|
xgbe_phy_kx_2500_mode(pdata);
|
|
break;
|
|
case XGBE_MODE_KR:
|
|
xgbe_phy_kr_mode(pdata);
|
|
break;
|
|
case XGBE_MODE_SGMII_100:
|
|
xgbe_phy_sgmii_100_mode(pdata);
|
|
break;
|
|
case XGBE_MODE_SGMII_1000:
|
|
xgbe_phy_sgmii_1000_mode(pdata);
|
|
break;
|
|
case XGBE_MODE_X:
|
|
xgbe_phy_x_mode(pdata);
|
|
break;
|
|
case XGBE_MODE_SFI:
|
|
xgbe_phy_sfi_mode(pdata);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
|
|
enum xgbe_mode mode, u32 advert)
|
|
{
|
|
if (pdata->phy.autoneg == AUTONEG_ENABLE) {
|
|
if (pdata->phy.advertising & advert)
|
|
return true;
|
|
} else {
|
|
enum xgbe_mode cur_mode;
|
|
|
|
cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
|
|
if (cur_mode == mode)
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
|
|
enum xgbe_mode mode)
|
|
{
|
|
switch (mode) {
|
|
case XGBE_MODE_X:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_1000baseT_Full);
|
|
case XGBE_MODE_KR:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_10000baseT_Full);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
|
|
enum xgbe_mode mode)
|
|
{
|
|
switch (mode) {
|
|
case XGBE_MODE_SGMII_100:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_100baseT_Full);
|
|
case XGBE_MODE_SGMII_1000:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_1000baseT_Full);
|
|
case XGBE_MODE_KR:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_10000baseT_Full);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
|
|
enum xgbe_mode mode)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
switch (mode) {
|
|
case XGBE_MODE_X:
|
|
if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
|
|
return false;
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_1000baseT_Full);
|
|
case XGBE_MODE_SGMII_100:
|
|
if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
|
|
return false;
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_100baseT_Full);
|
|
case XGBE_MODE_SGMII_1000:
|
|
if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
|
|
return false;
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_1000baseT_Full);
|
|
case XGBE_MODE_SFI:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_10000baseT_Full);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
|
|
enum xgbe_mode mode)
|
|
{
|
|
switch (mode) {
|
|
case XGBE_MODE_KX_2500:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_2500baseX_Full);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
|
|
enum xgbe_mode mode)
|
|
{
|
|
switch (mode) {
|
|
case XGBE_MODE_KX_1000:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_1000baseKX_Full);
|
|
case XGBE_MODE_KR:
|
|
return xgbe_phy_check_mode(pdata, mode,
|
|
ADVERTISED_10000baseKR_Full);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
switch (phy_data->port_mode) {
|
|
case XGBE_PORT_MODE_BACKPLANE:
|
|
return xgbe_phy_use_bp_mode(pdata, mode);
|
|
case XGBE_PORT_MODE_BACKPLANE_2500:
|
|
return xgbe_phy_use_bp_2500_mode(pdata, mode);
|
|
case XGBE_PORT_MODE_1000BASE_T:
|
|
case XGBE_PORT_MODE_NBASE_T:
|
|
case XGBE_PORT_MODE_10GBASE_T:
|
|
return xgbe_phy_use_baset_mode(pdata, mode);
|
|
case XGBE_PORT_MODE_1000BASE_X:
|
|
case XGBE_PORT_MODE_10GBASE_R:
|
|
return xgbe_phy_use_basex_mode(pdata, mode);
|
|
case XGBE_PORT_MODE_SFP:
|
|
return xgbe_phy_use_sfp_mode(pdata, mode);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
|
|
int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_1000:
|
|
return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
|
|
case SPEED_10000:
|
|
return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
|
|
int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_100:
|
|
case SPEED_1000:
|
|
return true;
|
|
case SPEED_10000:
|
|
return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
|
|
int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_100:
|
|
return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
|
|
case SPEED_1000:
|
|
return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
|
|
(phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
|
|
case SPEED_10000:
|
|
return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_2500:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_valid_speed_bp_mode(int speed)
|
|
{
|
|
switch (speed) {
|
|
case SPEED_1000:
|
|
case SPEED_10000:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
switch (phy_data->port_mode) {
|
|
case XGBE_PORT_MODE_BACKPLANE:
|
|
return xgbe_phy_valid_speed_bp_mode(speed);
|
|
case XGBE_PORT_MODE_BACKPLANE_2500:
|
|
return xgbe_phy_valid_speed_bp_2500_mode(speed);
|
|
case XGBE_PORT_MODE_1000BASE_T:
|
|
case XGBE_PORT_MODE_NBASE_T:
|
|
case XGBE_PORT_MODE_10GBASE_T:
|
|
return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
|
|
case XGBE_PORT_MODE_1000BASE_X:
|
|
case XGBE_PORT_MODE_10GBASE_R:
|
|
return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
|
|
case XGBE_PORT_MODE_SFP:
|
|
return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int ret, reg;
|
|
|
|
*an_restart = 0;
|
|
|
|
if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
|
|
/* Check SFP signals */
|
|
xgbe_phy_sfp_detect(pdata);
|
|
|
|
if (phy_data->sfp_changed) {
|
|
*an_restart = 1;
|
|
return 0;
|
|
}
|
|
|
|
if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
|
|
return 0;
|
|
}
|
|
|
|
if (phy_data->phydev) {
|
|
/* Check external PHY */
|
|
ret = phy_read_status(phy_data->phydev);
|
|
if (ret < 0)
|
|
return 0;
|
|
|
|
if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
|
|
!phy_aneg_done(phy_data->phydev))
|
|
return 0;
|
|
|
|
if (!phy_data->phydev->link)
|
|
return 0;
|
|
}
|
|
|
|
/* Link status is latched low, so read once to clear
|
|
* and then read again to get current state
|
|
*/
|
|
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
|
|
reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
|
|
if (reg & MDIO_STAT1_LSTATUS)
|
|
return 1;
|
|
|
|
/* No link, attempt a receiver reset cycle */
|
|
if (phy_data->rrc_count++) {
|
|
phy_data->rrc_count = 0;
|
|
xgbe_phy_rrc(pdata);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int reg;
|
|
|
|
reg = XP_IOREAD(pdata, XP_PROP_3);
|
|
|
|
phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
|
|
XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);
|
|
|
|
phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);
|
|
|
|
phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,
|
|
GPIO_RX_LOS);
|
|
phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,
|
|
GPIO_TX_FAULT);
|
|
phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,
|
|
GPIO_MOD_ABS);
|
|
phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,
|
|
GPIO_RATE_SELECT);
|
|
|
|
if (netif_msg_probe(pdata)) {
|
|
dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
|
|
phy_data->sfp_gpio_address);
|
|
dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
|
|
phy_data->sfp_gpio_mask);
|
|
dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
|
|
phy_data->sfp_gpio_rx_los);
|
|
dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
|
|
phy_data->sfp_gpio_tx_fault);
|
|
dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
|
|
phy_data->sfp_gpio_mod_absent);
|
|
dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
|
|
phy_data->sfp_gpio_rate_select);
|
|
}
|
|
}
|
|
|
|
static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int reg, mux_addr_hi, mux_addr_lo;
|
|
|
|
reg = XP_IOREAD(pdata, XP_PROP_4);
|
|
|
|
mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);
|
|
mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);
|
|
if (mux_addr_lo == XGBE_SFP_DIRECT)
|
|
return;
|
|
|
|
phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
|
|
phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
|
|
phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);
|
|
|
|
if (netif_msg_probe(pdata)) {
|
|
dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
|
|
phy_data->sfp_mux_address);
|
|
dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
|
|
phy_data->sfp_mux_channel);
|
|
}
|
|
}
|
|
|
|
static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
|
|
{
|
|
xgbe_phy_sfp_comm_setup(pdata);
|
|
xgbe_phy_sfp_gpio_setup(pdata);
|
|
}
|
|
|
|
static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int ret;
|
|
|
|
ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
u8 gpio_reg, gpio_ports[2], gpio_data[3];
|
|
int ret;
|
|
|
|
/* Read the output port registers */
|
|
gpio_reg = 2;
|
|
ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
|
|
&gpio_reg, sizeof(gpio_reg),
|
|
gpio_ports, sizeof(gpio_ports));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Prepare to write the GPIO data */
|
|
gpio_data[0] = 2;
|
|
gpio_data[1] = gpio_ports[0];
|
|
gpio_data[2] = gpio_ports[1];
|
|
|
|
/* Set the GPIO pin */
|
|
if (phy_data->mdio_reset_gpio < 8)
|
|
gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
|
|
else
|
|
gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
|
|
|
|
/* Write the output port registers */
|
|
ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
|
|
gpio_data, sizeof(gpio_data));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Clear the GPIO pin */
|
|
if (phy_data->mdio_reset_gpio < 8)
|
|
gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
|
|
else
|
|
gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
|
|
|
|
/* Write the output port registers */
|
|
ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
|
|
gpio_data, sizeof(gpio_data));
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
int ret;
|
|
|
|
if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
|
|
return 0;
|
|
|
|
ret = xgbe_phy_get_comm_ownership(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
|
|
ret = xgbe_phy_i2c_mdio_reset(pdata);
|
|
else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
|
|
ret = xgbe_phy_int_mdio_reset(pdata);
|
|
|
|
xgbe_phy_put_comm_ownership(pdata);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
unsigned int reg;
|
|
|
|
if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
|
|
return 0;
|
|
|
|
reg = XP_IOREAD(pdata, XP_PROP_3);
|
|
phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);
|
|
switch (phy_data->mdio_reset) {
|
|
case XGBE_MDIO_RESET_NONE:
|
|
case XGBE_MDIO_RESET_I2C_GPIO:
|
|
case XGBE_MDIO_RESET_INT_GPIO:
|
|
break;
|
|
default:
|
|
dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
|
|
phy_data->mdio_reset);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
|
|
phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
|
|
XP_GET_BITS(reg, XP_PROP_3,
|
|
MDIO_RESET_I2C_ADDR);
|
|
phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
|
|
MDIO_RESET_I2C_GPIO);
|
|
} else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
|
|
phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,
|
|
MDIO_RESET_INT_GPIO);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
switch (phy_data->port_mode) {
|
|
case XGBE_PORT_MODE_BACKPLANE:
|
|
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
|
|
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_BACKPLANE_2500:
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_1000BASE_T:
|
|
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
|
|
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_1000BASE_X:
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_NBASE_T:
|
|
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
|
|
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
|
|
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_10GBASE_T:
|
|
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
|
|
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
|
|
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_10GBASE_R:
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_SFP:
|
|
if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
|
|
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
|
|
(phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
|
|
return false;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
switch (phy_data->port_mode) {
|
|
case XGBE_PORT_MODE_BACKPLANE:
|
|
case XGBE_PORT_MODE_BACKPLANE_2500:
|
|
if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_1000BASE_T:
|
|
case XGBE_PORT_MODE_1000BASE_X:
|
|
case XGBE_PORT_MODE_NBASE_T:
|
|
case XGBE_PORT_MODE_10GBASE_T:
|
|
case XGBE_PORT_MODE_10GBASE_R:
|
|
if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
|
|
return false;
|
|
break;
|
|
case XGBE_PORT_MODE_SFP:
|
|
if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
|
|
return false;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
|
|
{
|
|
unsigned int reg;
|
|
|
|
reg = XP_IOREAD(pdata, XP_PROP_0);
|
|
if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))
|
|
return false;
|
|
if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
/* If we have an external PHY, free it */
|
|
xgbe_phy_free_phy_device(pdata);
|
|
|
|
/* Reset SFP data */
|
|
xgbe_phy_sfp_reset(phy_data);
|
|
xgbe_phy_sfp_mod_absent(pdata);
|
|
|
|
/* Power off the PHY */
|
|
xgbe_phy_power_off(pdata);
|
|
|
|
/* Stop the I2C controller */
|
|
pdata->i2c_if.i2c_stop(pdata);
|
|
}
|
|
|
|
static int xgbe_phy_start(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
int ret;
|
|
|
|
/* Start the I2C controller */
|
|
ret = pdata->i2c_if.i2c_start(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Start in highest supported mode */
|
|
xgbe_phy_set_mode(pdata, phy_data->start_mode);
|
|
|
|
/* After starting the I2C controller, we can check for an SFP */
|
|
switch (phy_data->port_mode) {
|
|
case XGBE_PORT_MODE_SFP:
|
|
xgbe_phy_sfp_detect(pdata);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* If we have an external PHY, start it */
|
|
ret = xgbe_phy_find_phy_device(pdata);
|
|
if (ret)
|
|
goto err_i2c;
|
|
|
|
return 0;
|
|
|
|
err_i2c:
|
|
pdata->i2c_if.i2c_stop(pdata);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
enum xgbe_mode cur_mode;
|
|
int ret;
|
|
|
|
/* Reset by power cycling the PHY */
|
|
cur_mode = phy_data->cur_mode;
|
|
xgbe_phy_power_off(pdata);
|
|
xgbe_phy_set_mode(pdata, cur_mode);
|
|
|
|
if (!phy_data->phydev)
|
|
return 0;
|
|
|
|
/* Reset the external PHY */
|
|
ret = xgbe_phy_mdio_reset(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return phy_init_hw(phy_data->phydev);
|
|
}
|
|
|
|
static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data = pdata->phy_data;
|
|
|
|
/* Unregister for driving external PHYs */
|
|
mdiobus_unregister(phy_data->mii);
|
|
}
|
|
|
|
static int xgbe_phy_init(struct xgbe_prv_data *pdata)
|
|
{
|
|
struct xgbe_phy_data *phy_data;
|
|
struct mii_bus *mii;
|
|
unsigned int reg;
|
|
int ret;
|
|
|
|
/* Check if enabled */
|
|
if (!xgbe_phy_port_enabled(pdata)) {
|
|
dev_info(pdata->dev, "device is not enabled\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Initialize the I2C controller */
|
|
ret = pdata->i2c_if.i2c_init(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
|
|
if (!phy_data)
|
|
return -ENOMEM;
|
|
pdata->phy_data = phy_data;
|
|
|
|
reg = XP_IOREAD(pdata, XP_PROP_0);
|
|
phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);
|
|
phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
|
|
phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);
|
|
phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);
|
|
phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);
|
|
if (netif_msg_probe(pdata)) {
|
|
dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
|
|
dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
|
|
dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
|
|
dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
|
|
dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
|
|
}
|
|
|
|
/* Validate the connection requested */
|
|
if (xgbe_phy_conn_type_mismatch(pdata)) {
|
|
dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
|
|
phy_data->port_mode, phy_data->conn_type);
|
|
}
|
|
|
|
/* Validate the mode requested */
|
|
if (xgbe_phy_port_mode_mismatch(pdata)) {
|
|
dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
|
|
phy_data->port_mode, phy_data->port_speeds);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Check for and validate MDIO reset support */
|
|
ret = xgbe_phy_mdio_reset_setup(pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Indicate current mode is unknown */
|
|
phy_data->cur_mode = XGBE_MODE_UNKNOWN;
|
|
|
|
/* Initialize supported features */
|
|
pdata->phy.supported = 0;
|
|
|
|
switch (phy_data->port_mode) {
|
|
/* Backplane support */
|
|
case XGBE_PORT_MODE_BACKPLANE:
|
|
pdata->phy.supported |= SUPPORTED_Autoneg;
|
|
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
pdata->phy.supported |= SUPPORTED_Backplane;
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
|
|
pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
|
|
phy_data->start_mode = XGBE_MODE_KX_1000;
|
|
}
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
|
|
pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
|
|
if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
|
|
pdata->phy.supported |=
|
|
SUPPORTED_10000baseR_FEC;
|
|
phy_data->start_mode = XGBE_MODE_KR;
|
|
}
|
|
|
|
phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
|
|
break;
|
|
case XGBE_PORT_MODE_BACKPLANE_2500:
|
|
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
pdata->phy.supported |= SUPPORTED_Backplane;
|
|
pdata->phy.supported |= SUPPORTED_2500baseX_Full;
|
|
phy_data->start_mode = XGBE_MODE_KX_2500;
|
|
|
|
phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
|
|
break;
|
|
|
|
/* MDIO 1GBase-T support */
|
|
case XGBE_PORT_MODE_1000BASE_T:
|
|
pdata->phy.supported |= SUPPORTED_Autoneg;
|
|
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
pdata->phy.supported |= SUPPORTED_TP;
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
|
|
pdata->phy.supported |= SUPPORTED_100baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SGMII_100;
|
|
}
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
|
|
pdata->phy.supported |= SUPPORTED_1000baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SGMII_1000;
|
|
}
|
|
|
|
phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
|
|
break;
|
|
|
|
/* MDIO Base-X support */
|
|
case XGBE_PORT_MODE_1000BASE_X:
|
|
pdata->phy.supported |= SUPPORTED_Autoneg;
|
|
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
pdata->phy.supported |= SUPPORTED_FIBRE;
|
|
pdata->phy.supported |= SUPPORTED_1000baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_X;
|
|
|
|
phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
|
|
break;
|
|
|
|
/* MDIO NBase-T support */
|
|
case XGBE_PORT_MODE_NBASE_T:
|
|
pdata->phy.supported |= SUPPORTED_Autoneg;
|
|
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
pdata->phy.supported |= SUPPORTED_TP;
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
|
|
pdata->phy.supported |= SUPPORTED_100baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SGMII_100;
|
|
}
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
|
|
pdata->phy.supported |= SUPPORTED_1000baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SGMII_1000;
|
|
}
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
|
|
pdata->phy.supported |= SUPPORTED_2500baseX_Full;
|
|
phy_data->start_mode = XGBE_MODE_KX_2500;
|
|
}
|
|
|
|
phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
|
|
break;
|
|
|
|
/* 10GBase-T support */
|
|
case XGBE_PORT_MODE_10GBASE_T:
|
|
pdata->phy.supported |= SUPPORTED_Autoneg;
|
|
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
pdata->phy.supported |= SUPPORTED_TP;
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
|
|
pdata->phy.supported |= SUPPORTED_100baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SGMII_100;
|
|
}
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
|
|
pdata->phy.supported |= SUPPORTED_1000baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SGMII_1000;
|
|
}
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
|
|
pdata->phy.supported |= SUPPORTED_10000baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_KR;
|
|
}
|
|
|
|
phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
|
|
break;
|
|
|
|
/* 10GBase-R support */
|
|
case XGBE_PORT_MODE_10GBASE_R:
|
|
pdata->phy.supported |= SUPPORTED_Autoneg;
|
|
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
pdata->phy.supported |= SUPPORTED_TP;
|
|
pdata->phy.supported |= SUPPORTED_10000baseT_Full;
|
|
if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
|
|
pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
|
|
phy_data->start_mode = XGBE_MODE_SFI;
|
|
|
|
phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
|
|
break;
|
|
|
|
/* SFP support */
|
|
case XGBE_PORT_MODE_SFP:
|
|
pdata->phy.supported |= SUPPORTED_Autoneg;
|
|
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
|
|
pdata->phy.supported |= SUPPORTED_TP;
|
|
pdata->phy.supported |= SUPPORTED_FIBRE;
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
|
|
pdata->phy.supported |= SUPPORTED_100baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SGMII_100;
|
|
}
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
|
|
pdata->phy.supported |= SUPPORTED_1000baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SGMII_1000;
|
|
}
|
|
if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
|
|
pdata->phy.supported |= SUPPORTED_10000baseT_Full;
|
|
phy_data->start_mode = XGBE_MODE_SFI;
|
|
if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
|
|
pdata->phy.supported |=
|
|
SUPPORTED_10000baseR_FEC;
|
|
}
|
|
|
|
phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
|
|
|
|
xgbe_phy_sfp_setup(pdata);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (netif_msg_probe(pdata))
|
|
dev_dbg(pdata->dev, "phy supported=%#x\n",
|
|
pdata->phy.supported);
|
|
|
|
/* Register for driving external PHYs */
|
|
mii = devm_mdiobus_alloc(pdata->dev);
|
|
if (!mii) {
|
|
dev_err(pdata->dev, "mdiobus_alloc failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mii->priv = pdata;
|
|
mii->name = "amd-xgbe-mii";
|
|
mii->read = xgbe_phy_mii_read;
|
|
mii->write = xgbe_phy_mii_write;
|
|
mii->parent = pdata->dev;
|
|
mii->phy_mask = ~0;
|
|
snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
|
|
ret = mdiobus_register(mii);
|
|
if (ret) {
|
|
dev_err(pdata->dev, "mdiobus_register failed\n");
|
|
return ret;
|
|
}
|
|
phy_data->mii = mii;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
|
|
{
|
|
struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
|
|
|
|
phy_impl->init = xgbe_phy_init;
|
|
phy_impl->exit = xgbe_phy_exit;
|
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phy_impl->reset = xgbe_phy_reset;
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phy_impl->start = xgbe_phy_start;
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phy_impl->stop = xgbe_phy_stop;
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phy_impl->link_status = xgbe_phy_link_status;
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phy_impl->valid_speed = xgbe_phy_valid_speed;
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phy_impl->use_mode = xgbe_phy_use_mode;
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phy_impl->set_mode = xgbe_phy_set_mode;
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phy_impl->get_mode = xgbe_phy_get_mode;
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phy_impl->switch_mode = xgbe_phy_switch_mode;
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phy_impl->cur_mode = xgbe_phy_cur_mode;
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phy_impl->an_mode = xgbe_phy_an_mode;
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phy_impl->an_config = xgbe_phy_an_config;
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phy_impl->an_outcome = xgbe_phy_an_outcome;
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}
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