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22cb7a3ac3
Add a new compatible string for the RZ/G1E (R8A7745) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
121 lines
4.5 KiB
Plaintext
121 lines
4.5 KiB
Plaintext
* Renesas Electronics Ethernet AVB
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This file provides information on what the device node for the Ethernet AVB
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interface contains.
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Required properties:
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- compatible: Must contain one or more of the following:
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- "renesas,etheravb-r8a7743" for the R8A7743 SoC.
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- "renesas,etheravb-r8a7745" for the R8A7745 SoC.
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- "renesas,etheravb-r8a7790" for the R8A7790 SoC.
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- "renesas,etheravb-r8a7791" for the R8A7791 SoC.
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- "renesas,etheravb-r8a7792" for the R8A7792 SoC.
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- "renesas,etheravb-r8a7793" for the R8A7793 SoC.
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- "renesas,etheravb-r8a7794" for the R8A7794 SoC.
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- "renesas,etheravb-rcar-gen2" as a fallback for the above
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R-Car Gen2 and RZ/G1 devices.
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- "renesas,etheravb-r8a7795" for the R8A7795 SoC.
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- "renesas,etheravb-r8a7796" for the R8A7796 SoC.
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- "renesas,etheravb-rcar-gen3" as a fallback for the above
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R-Car Gen3 devices.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first followed by
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the generic version.
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- reg: offset and length of (1) the register block and (2) the stream buffer.
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- interrupts: A list of interrupt-specifiers, one for each entry in
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interrupt-names.
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If interrupt-names is not present, an interrupt specifier
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for a single muxed interrupt.
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- phy-mode: see ethernet.txt file in the same directory.
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- phy-handle: see ethernet.txt file in the same directory.
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- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
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- #size-cells: number of size cells on the MDIO bus, must be equal to 0.
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- clocks: clock phandle and specifier pair.
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- pinctrl-0: phandle, referring to a default pin configuration node.
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Optional properties:
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- interrupt-parent: the phandle for the interrupt controller that services
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interrupts for this device.
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- interrupt-names: A list of interrupt names.
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For the R8A779[56] SoCs this property is mandatory;
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it should include one entry per channel, named "ch%u",
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where %u is the channel number ranging from 0 to 24.
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For other SoCs this property is optional; if present
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it should contain "mux" for a single muxed interrupt.
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- pinctrl-names: pin configuration state name ("default").
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- renesas,no-ether-link: boolean, specify when a board does not provide a proper
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AVB_LINK signal.
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- renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
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active-low instead of normal active-high.
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Example:
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ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3";
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reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19",
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"ch20", "ch21", "ch22", "ch23",
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"ch24";
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&cpg>;
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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pinctrl-0 = <ðer_pins>;
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pinctrl-names = "default";
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renesas,no-ether-link;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <900>;
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rxdv-skew-ps = <0>;
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rxd0-skew-ps = <0>;
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rxd1-skew-ps = <0>;
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rxd2-skew-ps = <0>;
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rxd3-skew-ps = <0>;
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txc-skew-ps = <900>;
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txen-skew-ps = <0>;
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txd0-skew-ps = <0>;
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txd1-skew-ps = <0>;
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txd2-skew-ps = <0>;
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txd3-skew-ps = <0>;
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reg = <0>;
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interrupt-parent = <&gpio2>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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