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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a750036f35
With the write lock path simply subtracting RW_LOCK_BIAS there is, on large systems, the theoretical possibility of overflowing the 32-bit value that was used so far (namely if 128 or more CPUs manage to do the subtraction, but don't get to do the inverse addition in the failure path quickly enough). A first measure is to modify RW_LOCK_BIAS itself - with the new value chosen, it is good for up to 2048 CPUs each allowed to nest over 2048 times on the read path without causing an issue. Quite possibly it would even be sufficient to adjust the bias a little further, assuming that allowing for significantly less nesting would suffice. However, as the original value chosen allowed for even more nesting levels, to support more than 2048 CPUs (possible currently only for 64-bit kernels) the lock itself gets widened to 64 bits. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/4E258E0D020000780004E3F0@nat28.tlf.novell.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
50 lines
1.0 KiB
C
50 lines
1.0 KiB
C
#ifndef _ASM_X86_RWLOCK_H
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#define _ASM_X86_RWLOCK_H
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#include <asm/asm.h>
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#if CONFIG_NR_CPUS <= 2048
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#ifndef __ASSEMBLY__
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typedef union {
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s32 lock;
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s32 write;
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} arch_rwlock_t;
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#endif
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#define RW_LOCK_BIAS 0x00100000
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#define READ_LOCK_SIZE(insn) __ASM_FORM(insn##l)
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#define READ_LOCK_ATOMIC(n) atomic_##n
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#define WRITE_LOCK_ADD(n) __ASM_FORM_COMMA(addl n)
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#define WRITE_LOCK_SUB(n) __ASM_FORM_COMMA(subl n)
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#define WRITE_LOCK_CMP RW_LOCK_BIAS
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#else /* CONFIG_NR_CPUS > 2048 */
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#include <linux/const.h>
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#ifndef __ASSEMBLY__
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typedef union {
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s64 lock;
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struct {
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u32 read;
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s32 write;
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};
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} arch_rwlock_t;
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#endif
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#define RW_LOCK_BIAS (_AC(1,L) << 32)
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#define READ_LOCK_SIZE(insn) __ASM_FORM(insn##q)
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#define READ_LOCK_ATOMIC(n) atomic64_##n
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#define WRITE_LOCK_ADD(n) __ASM_FORM(incl)
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#define WRITE_LOCK_SUB(n) __ASM_FORM(decl)
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#define WRITE_LOCK_CMP 1
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#endif /* CONFIG_NR_CPUS */
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#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
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/* Actual code is in asm/spinlock.h or in arch/x86/lib/rwlock.S */
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#endif /* _ASM_X86_RWLOCK_H */
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