mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 22:45:23 +07:00
72f793f14a
I'm going to hook vc4 up to the sphinx build, so clean up its comments to not generate warnings when we do. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20170227201144.10970-2-eric@anholt.net
980 lines
24 KiB
C
980 lines
24 KiB
C
/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include "uapi/drm/vc4_drm.h"
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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#include "vc4_trace.h"
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static void
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vc4_queue_hangcheck(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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mod_timer(&vc4->hangcheck.timer,
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round_jiffies_up(jiffies + msecs_to_jiffies(100)));
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}
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struct vc4_hang_state {
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struct drm_vc4_get_hang_state user_state;
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u32 bo_count;
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struct drm_gem_object **bo;
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};
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static void
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vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state)
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{
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unsigned int i;
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for (i = 0; i < state->user_state.bo_count; i++)
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drm_gem_object_unreference_unlocked(state->bo[i]);
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kfree(state);
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}
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int
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vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_vc4_get_hang_state *get_state = data;
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struct drm_vc4_get_hang_state_bo *bo_state;
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struct vc4_hang_state *kernel_state;
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struct drm_vc4_get_hang_state *state;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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unsigned long irqflags;
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u32 i;
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int ret = 0;
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spin_lock_irqsave(&vc4->job_lock, irqflags);
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kernel_state = vc4->hang_state;
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if (!kernel_state) {
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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return -ENOENT;
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}
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state = &kernel_state->user_state;
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/* If the user's array isn't big enough, just return the
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* required array size.
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*/
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if (get_state->bo_count < state->bo_count) {
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get_state->bo_count = state->bo_count;
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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return 0;
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}
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vc4->hang_state = NULL;
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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/* Save the user's BO pointer, so we don't stomp it with the memcpy. */
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state->bo = get_state->bo;
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memcpy(get_state, state, sizeof(*state));
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bo_state = kcalloc(state->bo_count, sizeof(*bo_state), GFP_KERNEL);
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if (!bo_state) {
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ret = -ENOMEM;
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goto err_free;
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}
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for (i = 0; i < state->bo_count; i++) {
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struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]);
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u32 handle;
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ret = drm_gem_handle_create(file_priv, kernel_state->bo[i],
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&handle);
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if (ret) {
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state->bo_count = i - 1;
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goto err;
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}
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bo_state[i].handle = handle;
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bo_state[i].paddr = vc4_bo->base.paddr;
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bo_state[i].size = vc4_bo->base.base.size;
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}
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if (copy_to_user((void __user *)(uintptr_t)get_state->bo,
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bo_state,
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state->bo_count * sizeof(*bo_state)))
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ret = -EFAULT;
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kfree(bo_state);
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err_free:
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vc4_free_hang_state(dev, kernel_state);
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err:
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return ret;
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}
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static void
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vc4_save_hang_state(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_vc4_get_hang_state *state;
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struct vc4_hang_state *kernel_state;
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struct vc4_exec_info *exec[2];
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struct vc4_bo *bo;
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unsigned long irqflags;
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unsigned int i, j, unref_list_count, prev_idx;
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kernel_state = kcalloc(1, sizeof(*kernel_state), GFP_KERNEL);
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if (!kernel_state)
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return;
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state = &kernel_state->user_state;
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spin_lock_irqsave(&vc4->job_lock, irqflags);
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exec[0] = vc4_first_bin_job(vc4);
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exec[1] = vc4_first_render_job(vc4);
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if (!exec[0] && !exec[1]) {
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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return;
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}
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/* Get the bos from both binner and renderer into hang state. */
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state->bo_count = 0;
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for (i = 0; i < 2; i++) {
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if (!exec[i])
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continue;
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unref_list_count = 0;
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list_for_each_entry(bo, &exec[i]->unref_list, unref_head)
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unref_list_count++;
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state->bo_count += exec[i]->bo_count + unref_list_count;
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}
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kernel_state->bo = kcalloc(state->bo_count,
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sizeof(*kernel_state->bo), GFP_ATOMIC);
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if (!kernel_state->bo) {
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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return;
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}
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prev_idx = 0;
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for (i = 0; i < 2; i++) {
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if (!exec[i])
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continue;
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for (j = 0; j < exec[i]->bo_count; j++) {
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drm_gem_object_reference(&exec[i]->bo[j]->base);
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kernel_state->bo[j + prev_idx] = &exec[i]->bo[j]->base;
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}
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list_for_each_entry(bo, &exec[i]->unref_list, unref_head) {
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drm_gem_object_reference(&bo->base.base);
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kernel_state->bo[j + prev_idx] = &bo->base.base;
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j++;
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}
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prev_idx = j + 1;
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}
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if (exec[0])
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state->start_bin = exec[0]->ct0ca;
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if (exec[1])
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state->start_render = exec[1]->ct1ca;
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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state->ct0ca = V3D_READ(V3D_CTNCA(0));
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state->ct0ea = V3D_READ(V3D_CTNEA(0));
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state->ct1ca = V3D_READ(V3D_CTNCA(1));
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state->ct1ea = V3D_READ(V3D_CTNEA(1));
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state->ct0cs = V3D_READ(V3D_CTNCS(0));
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state->ct1cs = V3D_READ(V3D_CTNCS(1));
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state->ct0ra0 = V3D_READ(V3D_CT00RA0);
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state->ct1ra0 = V3D_READ(V3D_CT01RA0);
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state->bpca = V3D_READ(V3D_BPCA);
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state->bpcs = V3D_READ(V3D_BPCS);
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state->bpoa = V3D_READ(V3D_BPOA);
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state->bpos = V3D_READ(V3D_BPOS);
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state->vpmbase = V3D_READ(V3D_VPMBASE);
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state->dbge = V3D_READ(V3D_DBGE);
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state->fdbgo = V3D_READ(V3D_FDBGO);
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state->fdbgb = V3D_READ(V3D_FDBGB);
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state->fdbgr = V3D_READ(V3D_FDBGR);
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state->fdbgs = V3D_READ(V3D_FDBGS);
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state->errstat = V3D_READ(V3D_ERRSTAT);
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spin_lock_irqsave(&vc4->job_lock, irqflags);
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if (vc4->hang_state) {
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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vc4_free_hang_state(dev, kernel_state);
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} else {
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vc4->hang_state = kernel_state;
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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}
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}
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static void
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vc4_reset(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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DRM_INFO("Resetting GPU.\n");
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mutex_lock(&vc4->power_lock);
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if (vc4->power_refcount) {
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/* Power the device off and back on the by dropping the
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* reference on runtime PM.
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*/
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pm_runtime_put_sync_suspend(&vc4->v3d->pdev->dev);
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pm_runtime_get_sync(&vc4->v3d->pdev->dev);
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}
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mutex_unlock(&vc4->power_lock);
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vc4_irq_reset(dev);
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/* Rearm the hangcheck -- another job might have been waiting
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* for our hung one to get kicked off, and vc4_irq_reset()
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* would have started it.
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*/
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vc4_queue_hangcheck(dev);
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}
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static void
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vc4_reset_work(struct work_struct *work)
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{
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struct vc4_dev *vc4 =
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container_of(work, struct vc4_dev, hangcheck.reset_work);
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vc4_save_hang_state(vc4->dev);
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vc4_reset(vc4->dev);
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}
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static void
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vc4_hangcheck_elapsed(unsigned long data)
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{
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struct drm_device *dev = (struct drm_device *)data;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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uint32_t ct0ca, ct1ca;
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unsigned long irqflags;
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struct vc4_exec_info *bin_exec, *render_exec;
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spin_lock_irqsave(&vc4->job_lock, irqflags);
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bin_exec = vc4_first_bin_job(vc4);
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render_exec = vc4_first_render_job(vc4);
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/* If idle, we can stop watching for hangs. */
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if (!bin_exec && !render_exec) {
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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return;
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}
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ct0ca = V3D_READ(V3D_CTNCA(0));
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ct1ca = V3D_READ(V3D_CTNCA(1));
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/* If we've made any progress in execution, rearm the timer
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* and wait.
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*/
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if ((bin_exec && ct0ca != bin_exec->last_ct0ca) ||
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(render_exec && ct1ca != render_exec->last_ct1ca)) {
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if (bin_exec)
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bin_exec->last_ct0ca = ct0ca;
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if (render_exec)
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render_exec->last_ct1ca = ct1ca;
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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vc4_queue_hangcheck(dev);
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return;
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}
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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/* We've gone too long with no progress, reset. This has to
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* be done from a work struct, since resetting can sleep and
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* this timer hook isn't allowed to.
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*/
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schedule_work(&vc4->hangcheck.reset_work);
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}
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static void
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submit_cl(struct drm_device *dev, uint32_t thread, uint32_t start, uint32_t end)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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/* Set the current and end address of the control list.
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* Writing the end register is what starts the job.
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*/
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V3D_WRITE(V3D_CTNCA(thread), start);
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V3D_WRITE(V3D_CTNEA(thread), end);
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}
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int
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vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, uint64_t timeout_ns,
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bool interruptible)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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int ret = 0;
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unsigned long timeout_expire;
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DEFINE_WAIT(wait);
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if (vc4->finished_seqno >= seqno)
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return 0;
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if (timeout_ns == 0)
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return -ETIME;
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timeout_expire = jiffies + nsecs_to_jiffies(timeout_ns);
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trace_vc4_wait_for_seqno_begin(dev, seqno, timeout_ns);
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for (;;) {
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prepare_to_wait(&vc4->job_wait_queue, &wait,
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interruptible ? TASK_INTERRUPTIBLE :
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TASK_UNINTERRUPTIBLE);
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if (interruptible && signal_pending(current)) {
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ret = -ERESTARTSYS;
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break;
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}
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if (vc4->finished_seqno >= seqno)
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break;
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if (timeout_ns != ~0ull) {
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if (time_after_eq(jiffies, timeout_expire)) {
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ret = -ETIME;
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break;
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}
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schedule_timeout(timeout_expire - jiffies);
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} else {
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schedule();
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}
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}
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finish_wait(&vc4->job_wait_queue, &wait);
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trace_vc4_wait_for_seqno_end(dev, seqno);
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return ret;
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}
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static void
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vc4_flush_caches(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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/* Flush the GPU L2 caches. These caches sit on top of system
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* L3 (the 128kb or so shared with the CPU), and are
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* non-allocating in the L3.
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*/
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V3D_WRITE(V3D_L2CACTL,
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V3D_L2CACTL_L2CCLR);
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V3D_WRITE(V3D_SLCACTL,
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VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
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VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) |
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VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
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VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
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}
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/* Sets the registers for the next job to be actually be executed in
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* the hardware.
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*
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* The job_lock should be held during this.
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*/
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void
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vc4_submit_next_bin_job(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_exec_info *exec;
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again:
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exec = vc4_first_bin_job(vc4);
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if (!exec)
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return;
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vc4_flush_caches(dev);
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/* Either put the job in the binner if it uses the binner, or
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* immediately move it to the to-be-rendered queue.
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*/
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if (exec->ct0ca != exec->ct0ea) {
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submit_cl(dev, 0, exec->ct0ca, exec->ct0ea);
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} else {
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vc4_move_job_to_render(dev, exec);
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goto again;
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}
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}
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void
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vc4_submit_next_render_job(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_exec_info *exec = vc4_first_render_job(vc4);
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if (!exec)
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return;
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submit_cl(dev, 1, exec->ct1ca, exec->ct1ea);
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}
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void
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vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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bool was_empty = list_empty(&vc4->render_job_list);
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list_move_tail(&exec->head, &vc4->render_job_list);
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if (was_empty)
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vc4_submit_next_render_job(dev);
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}
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static void
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vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno)
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{
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struct vc4_bo *bo;
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unsigned i;
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for (i = 0; i < exec->bo_count; i++) {
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bo = to_vc4_bo(&exec->bo[i]->base);
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bo->seqno = seqno;
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}
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list_for_each_entry(bo, &exec->unref_list, unref_head) {
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bo->seqno = seqno;
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}
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for (i = 0; i < exec->rcl_write_bo_count; i++) {
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bo = to_vc4_bo(&exec->rcl_write_bo[i]->base);
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bo->write_seqno = seqno;
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}
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}
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/* Queues a struct vc4_exec_info for execution. If no job is
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* currently executing, then submits it.
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*
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* Unlike most GPUs, our hardware only handles one command list at a
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* time. To queue multiple jobs at once, we'd need to edit the
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* previous command list to have a jump to the new one at the end, and
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* then bump the end address. That's a change for a later date,
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* though.
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*/
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static void
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vc4_queue_submit(struct drm_device *dev, struct vc4_exec_info *exec)
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
uint64_t seqno;
|
|
unsigned long irqflags;
|
|
|
|
spin_lock_irqsave(&vc4->job_lock, irqflags);
|
|
|
|
seqno = ++vc4->emit_seqno;
|
|
exec->seqno = seqno;
|
|
vc4_update_bo_seqnos(exec, seqno);
|
|
|
|
list_add_tail(&exec->head, &vc4->bin_job_list);
|
|
|
|
/* If no job was executing, kick ours off. Otherwise, it'll
|
|
* get started when the previous job's flush done interrupt
|
|
* occurs.
|
|
*/
|
|
if (vc4_first_bin_job(vc4) == exec) {
|
|
vc4_submit_next_bin_job(dev);
|
|
vc4_queue_hangcheck(dev);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
|
|
}
|
|
|
|
/**
|
|
* vc4_cl_lookup_bos() - Sets up exec->bo[] with the GEM objects
|
|
* referenced by the job.
|
|
* @dev: DRM device
|
|
* @file_priv: DRM file for this fd
|
|
* @exec: V3D job being set up
|
|
*
|
|
* The command validator needs to reference BOs by their index within
|
|
* the submitted job's BO list. This does the validation of the job's
|
|
* BO list and reference counting for the lifetime of the job.
|
|
*
|
|
* Note that this function doesn't need to unreference the BOs on
|
|
* failure, because that will happen at vc4_complete_exec() time.
|
|
*/
|
|
static int
|
|
vc4_cl_lookup_bos(struct drm_device *dev,
|
|
struct drm_file *file_priv,
|
|
struct vc4_exec_info *exec)
|
|
{
|
|
struct drm_vc4_submit_cl *args = exec->args;
|
|
uint32_t *handles;
|
|
int ret = 0;
|
|
int i;
|
|
|
|
exec->bo_count = args->bo_handle_count;
|
|
|
|
if (!exec->bo_count) {
|
|
/* See comment on bo_index for why we have to check
|
|
* this.
|
|
*/
|
|
DRM_ERROR("Rendering requires BOs to validate\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
exec->bo = drm_calloc_large(exec->bo_count,
|
|
sizeof(struct drm_gem_cma_object *));
|
|
if (!exec->bo) {
|
|
DRM_ERROR("Failed to allocate validated BO pointers\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
handles = drm_malloc_ab(exec->bo_count, sizeof(uint32_t));
|
|
if (!handles) {
|
|
ret = -ENOMEM;
|
|
DRM_ERROR("Failed to allocate incoming GEM handles\n");
|
|
goto fail;
|
|
}
|
|
|
|
if (copy_from_user(handles,
|
|
(void __user *)(uintptr_t)args->bo_handles,
|
|
exec->bo_count * sizeof(uint32_t))) {
|
|
ret = -EFAULT;
|
|
DRM_ERROR("Failed to copy in GEM handles\n");
|
|
goto fail;
|
|
}
|
|
|
|
spin_lock(&file_priv->table_lock);
|
|
for (i = 0; i < exec->bo_count; i++) {
|
|
struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
|
|
handles[i]);
|
|
if (!bo) {
|
|
DRM_ERROR("Failed to look up GEM BO %d: %d\n",
|
|
i, handles[i]);
|
|
ret = -EINVAL;
|
|
spin_unlock(&file_priv->table_lock);
|
|
goto fail;
|
|
}
|
|
drm_gem_object_reference(bo);
|
|
exec->bo[i] = (struct drm_gem_cma_object *)bo;
|
|
}
|
|
spin_unlock(&file_priv->table_lock);
|
|
|
|
fail:
|
|
drm_free_large(handles);
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec)
|
|
{
|
|
struct drm_vc4_submit_cl *args = exec->args;
|
|
void *temp = NULL;
|
|
void *bin;
|
|
int ret = 0;
|
|
uint32_t bin_offset = 0;
|
|
uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size,
|
|
16);
|
|
uint32_t uniforms_offset = shader_rec_offset + args->shader_rec_size;
|
|
uint32_t exec_size = uniforms_offset + args->uniforms_size;
|
|
uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) *
|
|
args->shader_rec_count);
|
|
struct vc4_bo *bo;
|
|
|
|
if (shader_rec_offset < args->bin_cl_size ||
|
|
uniforms_offset < shader_rec_offset ||
|
|
exec_size < uniforms_offset ||
|
|
args->shader_rec_count >= (UINT_MAX /
|
|
sizeof(struct vc4_shader_state)) ||
|
|
temp_size < exec_size) {
|
|
DRM_ERROR("overflow in exec arguments\n");
|
|
ret = -EINVAL;
|
|
goto fail;
|
|
}
|
|
|
|
/* Allocate space where we'll store the copied in user command lists
|
|
* and shader records.
|
|
*
|
|
* We don't just copy directly into the BOs because we need to
|
|
* read the contents back for validation, and I think the
|
|
* bo->vaddr is uncached access.
|
|
*/
|
|
temp = drm_malloc_ab(temp_size, 1);
|
|
if (!temp) {
|
|
DRM_ERROR("Failed to allocate storage for copying "
|
|
"in bin/render CLs.\n");
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
bin = temp + bin_offset;
|
|
exec->shader_rec_u = temp + shader_rec_offset;
|
|
exec->uniforms_u = temp + uniforms_offset;
|
|
exec->shader_state = temp + exec_size;
|
|
exec->shader_state_size = args->shader_rec_count;
|
|
|
|
if (copy_from_user(bin,
|
|
(void __user *)(uintptr_t)args->bin_cl,
|
|
args->bin_cl_size)) {
|
|
ret = -EFAULT;
|
|
goto fail;
|
|
}
|
|
|
|
if (copy_from_user(exec->shader_rec_u,
|
|
(void __user *)(uintptr_t)args->shader_rec,
|
|
args->shader_rec_size)) {
|
|
ret = -EFAULT;
|
|
goto fail;
|
|
}
|
|
|
|
if (copy_from_user(exec->uniforms_u,
|
|
(void __user *)(uintptr_t)args->uniforms,
|
|
args->uniforms_size)) {
|
|
ret = -EFAULT;
|
|
goto fail;
|
|
}
|
|
|
|
bo = vc4_bo_create(dev, exec_size, true);
|
|
if (IS_ERR(bo)) {
|
|
DRM_ERROR("Couldn't allocate BO for binning\n");
|
|
ret = PTR_ERR(bo);
|
|
goto fail;
|
|
}
|
|
exec->exec_bo = &bo->base;
|
|
|
|
list_add_tail(&to_vc4_bo(&exec->exec_bo->base)->unref_head,
|
|
&exec->unref_list);
|
|
|
|
exec->ct0ca = exec->exec_bo->paddr + bin_offset;
|
|
|
|
exec->bin_u = bin;
|
|
|
|
exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset;
|
|
exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset;
|
|
exec->shader_rec_size = args->shader_rec_size;
|
|
|
|
exec->uniforms_v = exec->exec_bo->vaddr + uniforms_offset;
|
|
exec->uniforms_p = exec->exec_bo->paddr + uniforms_offset;
|
|
exec->uniforms_size = args->uniforms_size;
|
|
|
|
ret = vc4_validate_bin_cl(dev,
|
|
exec->exec_bo->vaddr + bin_offset,
|
|
bin,
|
|
exec);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
ret = vc4_validate_shader_recs(dev, exec);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
/* Block waiting on any previous rendering into the CS's VBO,
|
|
* IB, or textures, so that pixels are actually written by the
|
|
* time we try to read them.
|
|
*/
|
|
ret = vc4_wait_for_seqno(dev, exec->bin_dep_seqno, ~0ull, true);
|
|
|
|
fail:
|
|
drm_free_large(temp);
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec)
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
unsigned i;
|
|
|
|
if (exec->bo) {
|
|
for (i = 0; i < exec->bo_count; i++)
|
|
drm_gem_object_unreference_unlocked(&exec->bo[i]->base);
|
|
drm_free_large(exec->bo);
|
|
}
|
|
|
|
while (!list_empty(&exec->unref_list)) {
|
|
struct vc4_bo *bo = list_first_entry(&exec->unref_list,
|
|
struct vc4_bo, unref_head);
|
|
list_del(&bo->unref_head);
|
|
drm_gem_object_unreference_unlocked(&bo->base.base);
|
|
}
|
|
|
|
mutex_lock(&vc4->power_lock);
|
|
if (--vc4->power_refcount == 0) {
|
|
pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
|
|
pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);
|
|
}
|
|
mutex_unlock(&vc4->power_lock);
|
|
|
|
kfree(exec);
|
|
}
|
|
|
|
void
|
|
vc4_job_handle_completed(struct vc4_dev *vc4)
|
|
{
|
|
unsigned long irqflags;
|
|
struct vc4_seqno_cb *cb, *cb_temp;
|
|
|
|
spin_lock_irqsave(&vc4->job_lock, irqflags);
|
|
while (!list_empty(&vc4->job_done_list)) {
|
|
struct vc4_exec_info *exec =
|
|
list_first_entry(&vc4->job_done_list,
|
|
struct vc4_exec_info, head);
|
|
list_del(&exec->head);
|
|
|
|
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
|
|
vc4_complete_exec(vc4->dev, exec);
|
|
spin_lock_irqsave(&vc4->job_lock, irqflags);
|
|
}
|
|
|
|
list_for_each_entry_safe(cb, cb_temp, &vc4->seqno_cb_list, work.entry) {
|
|
if (cb->seqno <= vc4->finished_seqno) {
|
|
list_del_init(&cb->work.entry);
|
|
schedule_work(&cb->work);
|
|
}
|
|
}
|
|
|
|
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
|
|
}
|
|
|
|
static void vc4_seqno_cb_work(struct work_struct *work)
|
|
{
|
|
struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work);
|
|
|
|
cb->func(cb);
|
|
}
|
|
|
|
int vc4_queue_seqno_cb(struct drm_device *dev,
|
|
struct vc4_seqno_cb *cb, uint64_t seqno,
|
|
void (*func)(struct vc4_seqno_cb *cb))
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
int ret = 0;
|
|
unsigned long irqflags;
|
|
|
|
cb->func = func;
|
|
INIT_WORK(&cb->work, vc4_seqno_cb_work);
|
|
|
|
spin_lock_irqsave(&vc4->job_lock, irqflags);
|
|
if (seqno > vc4->finished_seqno) {
|
|
cb->seqno = seqno;
|
|
list_add_tail(&cb->work.entry, &vc4->seqno_cb_list);
|
|
} else {
|
|
schedule_work(&cb->work);
|
|
}
|
|
spin_unlock_irqrestore(&vc4->job_lock, irqflags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Scheduled when any job has been completed, this walks the list of
|
|
* jobs that had completed and unrefs their BOs and frees their exec
|
|
* structs.
|
|
*/
|
|
static void
|
|
vc4_job_done_work(struct work_struct *work)
|
|
{
|
|
struct vc4_dev *vc4 =
|
|
container_of(work, struct vc4_dev, job_done_work);
|
|
|
|
vc4_job_handle_completed(vc4);
|
|
}
|
|
|
|
static int
|
|
vc4_wait_for_seqno_ioctl_helper(struct drm_device *dev,
|
|
uint64_t seqno,
|
|
uint64_t *timeout_ns)
|
|
{
|
|
unsigned long start = jiffies;
|
|
int ret = vc4_wait_for_seqno(dev, seqno, *timeout_ns, true);
|
|
|
|
if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) {
|
|
uint64_t delta = jiffies_to_nsecs(jiffies - start);
|
|
|
|
if (*timeout_ns >= delta)
|
|
*timeout_ns -= delta;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int
|
|
vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct drm_vc4_wait_seqno *args = data;
|
|
|
|
return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno,
|
|
&args->timeout_ns);
|
|
}
|
|
|
|
int
|
|
vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
int ret;
|
|
struct drm_vc4_wait_bo *args = data;
|
|
struct drm_gem_object *gem_obj;
|
|
struct vc4_bo *bo;
|
|
|
|
if (args->pad != 0)
|
|
return -EINVAL;
|
|
|
|
gem_obj = drm_gem_object_lookup(file_priv, args->handle);
|
|
if (!gem_obj) {
|
|
DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
|
|
return -EINVAL;
|
|
}
|
|
bo = to_vc4_bo(gem_obj);
|
|
|
|
ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno,
|
|
&args->timeout_ns);
|
|
|
|
drm_gem_object_unreference_unlocked(gem_obj);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* vc4_submit_cl_ioctl() - Submits a job (frame) to the VC4.
|
|
* @dev: DRM device
|
|
* @data: ioctl argument
|
|
* @file_priv: DRM file for this fd
|
|
*
|
|
* This is the main entrypoint for userspace to submit a 3D frame to
|
|
* the GPU. Userspace provides the binner command list (if
|
|
* applicable), and the kernel sets up the render command list to draw
|
|
* to the framebuffer described in the ioctl, using the command lists
|
|
* that the 3D engine's binner will produce.
|
|
*/
|
|
int
|
|
vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
struct drm_vc4_submit_cl *args = data;
|
|
struct vc4_exec_info *exec;
|
|
int ret = 0;
|
|
|
|
if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
|
|
DRM_ERROR("Unknown flags: 0x%02x\n", args->flags);
|
|
return -EINVAL;
|
|
}
|
|
|
|
exec = kcalloc(1, sizeof(*exec), GFP_KERNEL);
|
|
if (!exec) {
|
|
DRM_ERROR("malloc failure on exec struct\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mutex_lock(&vc4->power_lock);
|
|
if (vc4->power_refcount++ == 0)
|
|
ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
|
|
mutex_unlock(&vc4->power_lock);
|
|
if (ret < 0) {
|
|
kfree(exec);
|
|
return ret;
|
|
}
|
|
|
|
exec->args = args;
|
|
INIT_LIST_HEAD(&exec->unref_list);
|
|
|
|
ret = vc4_cl_lookup_bos(dev, file_priv, exec);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
if (exec->args->bin_cl_size != 0) {
|
|
ret = vc4_get_bcl(dev, exec);
|
|
if (ret)
|
|
goto fail;
|
|
} else {
|
|
exec->ct0ca = 0;
|
|
exec->ct0ea = 0;
|
|
}
|
|
|
|
ret = vc4_get_rcl(dev, exec);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
/* Clear this out of the struct we'll be putting in the queue,
|
|
* since it's part of our stack.
|
|
*/
|
|
exec->args = NULL;
|
|
|
|
vc4_queue_submit(dev, exec);
|
|
|
|
/* Return the seqno for our job. */
|
|
args->seqno = vc4->emit_seqno;
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
vc4_complete_exec(vc4->dev, exec);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
vc4_gem_init(struct drm_device *dev)
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
INIT_LIST_HEAD(&vc4->bin_job_list);
|
|
INIT_LIST_HEAD(&vc4->render_job_list);
|
|
INIT_LIST_HEAD(&vc4->job_done_list);
|
|
INIT_LIST_HEAD(&vc4->seqno_cb_list);
|
|
spin_lock_init(&vc4->job_lock);
|
|
|
|
INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work);
|
|
setup_timer(&vc4->hangcheck.timer,
|
|
vc4_hangcheck_elapsed,
|
|
(unsigned long)dev);
|
|
|
|
INIT_WORK(&vc4->job_done_work, vc4_job_done_work);
|
|
|
|
mutex_init(&vc4->power_lock);
|
|
}
|
|
|
|
void
|
|
vc4_gem_destroy(struct drm_device *dev)
|
|
{
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
/* Waiting for exec to finish would need to be done before
|
|
* unregistering V3D.
|
|
*/
|
|
WARN_ON(vc4->emit_seqno != vc4->finished_seqno);
|
|
|
|
/* V3D should already have disabled its interrupt and cleared
|
|
* the overflow allocation registers. Now free the object.
|
|
*/
|
|
if (vc4->overflow_mem) {
|
|
drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
|
|
vc4->overflow_mem = NULL;
|
|
}
|
|
|
|
if (vc4->hang_state)
|
|
vc4_free_hang_state(dev, vc4->hang_state);
|
|
|
|
vc4_bo_cache_destroy(dev);
|
|
}
|