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As per Am335x Errata [1] Advisory 1.0.9, The CPSW C0_TX_PEND and C0_RX_PEND interrupt outputs provide a single transmit interrupt that combines transmit channel interrupts TXPEND[7:0] and a single receive interrupt that combines receive channel interrupts RXPEND[7:0]. The TXPEND[0] and RXPEND[0] interrupt outputs are connected to the ARM Cortex-A8 interrupt controller (INTC) rather than the C0_TX_PEND and C0_RX_PEND interrupt outputs. So even though CPSW interrupt is cleared by writing appropriate values to EOI register the interrupt is not cleared in IRQ controller. So interrupt is still pending and CPU is struck in ISR, the workaround is to disable the interrupts in ARM irq controller. [1] http://www.ti.com/lit/er/sprz360f/sprz360f.pdf Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| cpmac.c | ||
| cpsw_ale.c | ||
| cpsw_ale.h | ||
| cpsw-common.c | ||
| cpsw-phy-sel.c | ||
| cpsw.c | ||
| cpsw.h | ||
| cpts.c | ||
| cpts.h | ||
| davinci_cpdma.c | ||
| davinci_cpdma.h | ||
| davinci_emac.c | ||
| davinci_mdio.c | ||
| Kconfig | ||
| Makefile | ||
| netcp_core.c | ||
| netcp_ethss.c | ||
| netcp_sgmii.c | ||
| netcp_xgbepcsr.c | ||
| netcp.h | ||
| tlan.c | ||
| tlan.h | ||