Zhenyu Wang 72a7a9925e drm/i915/gvt: Fix kernel oops for 3-level ppgtt guest ... As i915 won't allocate extra PDP for current default PML4 table, so for 3-level ppgtt guest, we would hit kernel pointer access failure on extra PDP pointers. So this trys to bypass that now. It won't impact real shadow PPGTT setup, so guest context still works. This is verified on 4.15 guest kernel with i915.enable_ppgtt=1 to force on old aliasing ppgtt behavior. Fixes: 4f15665ccb ("drm/i915: Add ppgtt to GVT GEM context") Reviewed-by: Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20200506095918.124913-1-zhenyuw@linux.intel.com		2020-05-11 17:07:25 +08:00
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drm	drm/i915/gvt: Fix kernel oops for 3-level ppgtt guest	2020-05-11 17:07:25 +08:00
host1x	drm/tegra: Fixes for v5.6-rc1	2020-02-07 12:22:30 +10:00
ipu-v3
trace	gpu/trace: add a gpu total memory usage tracepoint	2020-03-03 17:52:41 -05:00
vga
Makefile	gpu/trace: add a gpu total memory usage tracepoint	2020-03-03 17:52:41 -05:00