mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 03:47:32 +07:00
5d8a00eee2
to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCAAGBQJYsLxxAAoJEK0CiJfG5JUl0p0P/AiBaYvrmHBx3H9jdC3iQxd2 7luFN3OqpykmZc3xx2xO3WaZ96kwwxiMu8sj3+VQo6oCkEuOY2ru6uPiDOcF4P3+ 8ku2taoWlESDbVLebVTNJoRXBaBLaV+9BCN7AKvXpVw+/UkJI5hgr0yMdh4tgtvu K08tTMkDNDbA33KXuJo8/chQFqi2W6XBXk22YMkqqA8jx0F4EM759LcgUlD1YfBS HKkgSOgsW3Zwhl27ZEAJMthcmS4+wFaEgFBeipg/hxTLI3aQtmDtRfXwg0wkbBx2 8sVz9SyBwkjOT9+41kve+Je94NK3blnJEjbxPASveMwyhdX1TlDQCPfrXya/1zxz N1By1NpA6iEYwi4hy+OtBYlcsBHztAM/+eljDY2kEDvfiKjMa44GYmgBu4n8pq+n 75NJxws6ZkzPs5/QsLT3hvTaL1SNX6PaEW8HabDXO40ccZc4CYvFZVOXMAnKaXzZ 31hj8EvQ5x6hci+SPYyVu6j3ipOxN96VcZqEJ+hWyyuZEMK6Up1o/0lGZFgwa0UD SIl7RiTFKO6ko+8hYlk1g0DGtEyWDsdso1Bw4zaHwMngM/CwjJVzpK5T2t1fJyEh lN5MdhcOi0nsiRWdRxOwOlHDLf93qSo87mvseU1MCEXYN1aqTV3VxSm1YU8ZgQVk sAjpsJqj45enfDa9BmIt =o8o/ -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
746 lines
20 KiB
Plaintext
746 lines
20 KiB
Plaintext
/*
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* Copyright 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton64.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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#include <dt-bindings/clock/sun9i-a80-ccu.h>
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#include <dt-bindings/clock/sun9i-a80-de.h>
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#include <dt-bindings/clock/sun9i-a80-usb.h>
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#include <dt-bindings/reset/sun9i-a80-ccu.h>
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#include <dt-bindings/reset/sun9i-a80-de.h>
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#include <dt-bindings/reset/sun9i-a80-usb.h>
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/ {
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x1>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0x3>;
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};
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cpu4: cpu@100 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0x100>;
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};
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cpu5: cpu@101 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0x101>;
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};
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cpu6: cpu@102 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0x102>;
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};
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cpu7: cpu@103 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0x103>;
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};
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};
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memory {
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/* 8GB max. with LPAE */
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reg = <0 0x20000000 0x02 0>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <24000000>;
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arm,cpu-registers-not-fw-configured;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* map 64 bit address range down to 32 bits,
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* as the peripherals are all under 512MB.
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*/
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ranges = <0 0 0 0x20000000>;
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/*
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* This clock is actually configurable from the PRCM address
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* space. The external 24M oscillator can be turned off, and
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* the clock switched to an internal 16M RC oscillator. Under
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* normal operation there's no reason to do this, and the
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* default is to use the external good one, so just model this
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* as a fixed clock. Also it is not entirely clear if the
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* osc24M mux in the PRCM affects the entire clock tree, which
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* would also throw all the PLL clock rates off, or just the
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* downstream clocks in the PRCM.
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*/
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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/*
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* The 32k clock is from an external source, normally the
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* AC100 codec/RTC chip. This serves as a placeholder for
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* board dts files to specify the source.
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*/
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "osc32k";
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};
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cpus_clk: clk@08001410 {
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compatible = "allwinner,sun9i-a80-cpus-clk";
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reg = <0x08001410 0x4>;
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#clock-cells = <0>;
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clocks = <&osc32k>, <&osc24M>,
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<&ccu CLK_PLL_PERIPH0>,
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<&ccu CLK_PLL_AUDIO>;
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clock-output-names = "cpus";
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};
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ahbs: ahbs_clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&cpus_clk>;
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clock-output-names = "ahbs";
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};
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apbs: clk@0800141c {
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compatible = "allwinner,sun8i-a23-apb0-clk";
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reg = <0x0800141c 0x4>;
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#clock-cells = <0>;
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clocks = <&ahbs>;
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clock-output-names = "apbs";
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};
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apbs_gates: clk@08001428 {
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compatible = "allwinner,sun9i-a80-apbs-gates-clk";
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reg = <0x08001428 0x4>;
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#clock-cells = <1>;
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clocks = <&apbs>;
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clock-indices = <0>, <1>,
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<2>, <3>,
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<4>, <5>,
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<6>, <7>,
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<12>, <13>,
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<16>, <17>,
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<18>, <20>;
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clock-output-names = "apbs_pio", "apbs_ir",
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"apbs_timer", "apbs_rsb",
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"apbs_uart", "apbs_1wire",
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"apbs_i2c0", "apbs_i2c1",
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"apbs_ps2_0", "apbs_ps2_1",
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"apbs_dma", "apbs_i2s0",
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"apbs_i2s1", "apbs_twd";
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};
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r_1wire_clk: clk@08001450 {
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reg = <0x08001450 0x4>;
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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clocks = <&osc32k>, <&osc24M>;
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clock-output-names = "r_1wire";
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};
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r_ir_clk: clk@08001454 {
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reg = <0x08001454 0x4>;
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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clocks = <&osc32k>, <&osc24M>;
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clock-output-names = "r_ir";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* map 64 bit address range down to 32 bits,
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* as the peripherals are all under 512MB.
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*/
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ranges = <0 0 0 0x20000000>;
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ehci0: usb@00a00000 {
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compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
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reg = <0x00a00000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_clocks CLK_BUS_HCI0>;
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resets = <&usb_clocks RST_USB0_HCI>;
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phys = <&usbphy1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci0: usb@00a00400 {
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compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
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reg = <0x00a00400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_clocks CLK_BUS_HCI0>,
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<&usb_clocks CLK_USB_OHCI0>;
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resets = <&usb_clocks RST_USB0_HCI>;
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phys = <&usbphy1>;
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phy-names = "usb";
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status = "disabled";
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};
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usbphy1: phy@00a00800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a00800 0x4>;
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clocks = <&usb_clocks CLK_USB0_PHY>;
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clock-names = "phy";
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resets = <&usb_clocks RST_USB0_PHY>;
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reset-names = "phy";
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status = "disabled";
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#phy-cells = <0>;
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};
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ehci1: usb@00a01000 {
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compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
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reg = <0x00a01000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_clocks CLK_BUS_HCI1>;
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resets = <&usb_clocks RST_USB1_HCI>;
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phys = <&usbphy2>;
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phy-names = "usb";
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status = "disabled";
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};
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usbphy2: phy@00a01800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a01800 0x4>;
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clocks = <&usb_clocks CLK_USB1_HSIC>,
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<&usb_clocks CLK_USB_HSIC>,
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<&usb_clocks CLK_USB1_PHY>;
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clock-names = "hsic_480M",
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"hsic_12M",
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"phy";
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resets = <&usb_clocks RST_USB1_HSIC>,
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<&usb_clocks RST_USB1_PHY>;
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reset-names = "hsic",
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"phy";
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status = "disabled";
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#phy-cells = <0>;
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/* usb1 is always used with HSIC */
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phy_type = "hsic";
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};
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ehci2: usb@00a02000 {
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compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
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reg = <0x00a02000 0x100>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_clocks CLK_BUS_HCI2>;
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resets = <&usb_clocks RST_USB2_HCI>;
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phys = <&usbphy3>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci2: usb@00a02400 {
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compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
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reg = <0x00a02400 0x100>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_clocks CLK_BUS_HCI2>,
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<&usb_clocks CLK_USB_OHCI2>;
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resets = <&usb_clocks RST_USB2_HCI>;
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phys = <&usbphy3>;
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phy-names = "usb";
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status = "disabled";
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};
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usbphy3: phy@00a02800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a02800 0x4>;
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clocks = <&usb_clocks CLK_USB2_HSIC>,
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<&usb_clocks CLK_USB_HSIC>,
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<&usb_clocks CLK_USB2_PHY>;
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clock-names = "hsic_480M",
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"hsic_12M",
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"phy";
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resets = <&usb_clocks RST_USB2_HSIC>,
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<&usb_clocks RST_USB2_PHY>;
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reset-names = "hsic",
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"phy";
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status = "disabled";
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#phy-cells = <0>;
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};
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usb_clocks: clock@00a08000 {
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compatible = "allwinner,sun9i-a80-usb-clks";
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reg = <0x00a08000 0x8>;
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clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
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clock-names = "bus", "hosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun9i-a80-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
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<&ccu CLK_MMC0_OUTPUT>,
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<&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb", "mmc", "output", "sample";
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resets = <&mmc_config_clk 0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun9i-a80-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
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<&ccu CLK_MMC1_OUTPUT>,
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<&ccu CLK_MMC1_SAMPLE>;
|
|
clock-names = "ahb", "mmc", "output", "sample";
|
|
resets = <&mmc_config_clk 1>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc2: mmc@01c11000 {
|
|
compatible = "allwinner,sun9i-a80-mmc";
|
|
reg = <0x01c11000 0x1000>;
|
|
clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
|
|
<&ccu CLK_MMC2_OUTPUT>,
|
|
<&ccu CLK_MMC2_SAMPLE>;
|
|
clock-names = "ahb", "mmc", "output", "sample";
|
|
resets = <&mmc_config_clk 2>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc3: mmc@01c12000 {
|
|
compatible = "allwinner,sun9i-a80-mmc";
|
|
reg = <0x01c12000 0x1000>;
|
|
clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
|
|
<&ccu CLK_MMC3_OUTPUT>,
|
|
<&ccu CLK_MMC3_SAMPLE>;
|
|
clock-names = "ahb", "mmc", "output", "sample";
|
|
resets = <&mmc_config_clk 3>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc_config_clk: clk@01c13000 {
|
|
compatible = "allwinner,sun9i-a80-mmc-config-clk";
|
|
reg = <0x01c13000 0x10>;
|
|
clocks = <&ccu CLK_BUS_MMC>;
|
|
clock-names = "ahb";
|
|
resets = <&ccu RST_BUS_MMC>;
|
|
reset-names = "ahb";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
clock-output-names = "mmc0_config", "mmc1_config",
|
|
"mmc2_config", "mmc3_config";
|
|
};
|
|
|
|
gic: interrupt-controller@01c41000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c41000 0x1000>,
|
|
<0x01c42000 0x2000>,
|
|
<0x01c44000 0x2000>,
|
|
<0x01c46000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
de_clocks: clock@03000000 {
|
|
compatible = "allwinner,sun9i-a80-de-clks";
|
|
reg = <0x03000000 0x30>;
|
|
clocks = <&ccu CLK_DE>,
|
|
<&ccu CLK_SDRAM>,
|
|
<&ccu CLK_BUS_DE>;
|
|
clock-names = "mod",
|
|
"dram",
|
|
"bus";
|
|
resets = <&ccu RST_BUS_DE>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
ccu: clock@06000000 {
|
|
compatible = "allwinner,sun9i-a80-ccu";
|
|
reg = <0x06000000 0x800>;
|
|
clocks = <&osc24M>, <&osc32k>;
|
|
clock-names = "hosc", "losc";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
timer@06000c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x06000c00 0xa0>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt: watchdog@06000ca0 {
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
reg = <0x06000ca0 0x20>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pio: pinctrl@06000800 {
|
|
compatible = "allwinner,sun9i-a80-pinctrl";
|
|
reg = <0x06000800 0x400>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#size-cells = <0>;
|
|
#gpio-cells = <3>;
|
|
|
|
i2c3_pins_a: i2c3@0 {
|
|
pins = "PG10", "PG11";
|
|
function = "i2c3";
|
|
};
|
|
|
|
mmc0_pins: mmc0 {
|
|
pins = "PF0", "PF1" ,"PF2", "PF3",
|
|
"PF4", "PF5";
|
|
function = "mmc0";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
mmc1_pins: mmc1 {
|
|
pins = "PG0", "PG1" ,"PG2", "PG3",
|
|
"PG4", "PG5";
|
|
function = "mmc1";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
mmc2_8bit_pins: mmc2_8bit {
|
|
pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11", "PC12",
|
|
"PC13", "PC14", "PC15",
|
|
"PC16";
|
|
function = "mmc2";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
pins = "PH12", "PH13";
|
|
function = "uart0";
|
|
};
|
|
|
|
uart4_pins_a: uart4@0 {
|
|
pins = "PG12", "PG13", "PG14", "PG15";
|
|
function = "uart4";
|
|
};
|
|
};
|
|
|
|
uart0: serial@07000000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x07000000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
|
resets = <&ccu RST_BUS_UART0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@07000400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x07000400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
|
resets = <&ccu RST_BUS_UART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@07000800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x07000800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
|
resets = <&ccu RST_BUS_UART2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@07000c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x07000c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART3>;
|
|
resets = <&ccu RST_BUS_UART3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@07001000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x07001000 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART4>;
|
|
resets = <&ccu RST_BUS_UART4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@07001400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x07001400 0x400>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART5>;
|
|
resets = <&ccu RST_BUS_UART5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@07002800 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x07002800 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C0>;
|
|
resets = <&ccu RST_BUS_I2C0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@07002c00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x07002c00 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C1>;
|
|
resets = <&ccu RST_BUS_I2C1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@07003000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x07003000 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C2>;
|
|
resets = <&ccu RST_BUS_I2C2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c3: i2c@07003400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x07003400 0x400>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C3>;
|
|
resets = <&ccu RST_BUS_I2C3>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c4: i2c@07003800 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x07003800 0x400>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C4>;
|
|
resets = <&ccu RST_BUS_I2C4>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
r_wdt: watchdog@08001000 {
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
reg = <0x08001000 0x20>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
apbs_rst: reset@080014b0 {
|
|
reg = <0x080014b0 0x4>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
nmi_intc: interrupt-controller@080015a0 {
|
|
compatible = "allwinner,sun9i-a80-nmi";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x080015a0 0xc>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
r_ir: ir@08002000 {
|
|
compatible = "allwinner,sun5i-a13-ir";
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_ir_pins>;
|
|
clocks = <&apbs_gates 1>, <&r_ir_clk>;
|
|
clock-names = "apb", "ir";
|
|
resets = <&apbs_rst 1>;
|
|
reg = <0x08002000 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_uart: serial@08002800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x08002800 0x400>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apbs_gates 4>;
|
|
resets = <&apbs_rst 4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_pio: pinctrl@08002c00 {
|
|
compatible = "allwinner,sun9i-a80-r-pinctrl";
|
|
reg = <0x08002c00 0x400>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
resets = <&apbs_rst 0>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
r_ir_pins: r_ir {
|
|
pins = "PL6";
|
|
function = "s_cir_rx";
|
|
};
|
|
|
|
r_rsb_pins: r_rsb {
|
|
pins = "PN0", "PN1";
|
|
function = "s_rsb";
|
|
drive-strength = <20>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
r_rsb: i2c@08003400 {
|
|
compatible = "allwinner,sun8i-a23-rsb";
|
|
reg = <0x08003400 0x400>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apbs_gates 3>;
|
|
clock-frequency = <3000000>;
|
|
resets = <&apbs_rst 3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_rsb_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|