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60263dcd82
Till now we used clockevent from generic ARC driver. This was enough as long as we worked with simple multicore SoC. When we are working with multithread SoC each HW thread can be scheduled to receive timer interrupt using timer mask register. This patch will provide a way to control clock events per HW thread. The design idea is that for each core there is dedicated register (TSI) serving all 16 HW threads. The register is a bitmask with one bit for each HW thread. When HW thread wants that next expiration of timer interrupt will hit it then the proper bit should be set in this dedicated register. When timer expires all HW threads within this core which their bit is set at the TSI register will be interrupted. Driver can be used from device tree by: compatible = "ezchip,nps400-timer0" <-- for clocksource compatible = "ezchip,nps400-timer1" <-- for clockevent Note that name convention for timer0/timer1 was taken from legacy ARC design. This design is our base before adding HW threads. For backward compatibility we keep "ezchip,nps400-timer" for clocksource Signed-off-by: Noam Camus <noamca@mellanox.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Rob Herring <robh@kernel.org>
16 lines
298 B
Plaintext
16 lines
298 B
Plaintext
NPS Network Processor
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Required properties:
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- compatible : should be "ezchip,nps400-timer1"
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Clocks required for compatible = "ezchip,nps400-timer1":
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- clocks : Must contain a single entry describing the clock input
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Example:
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timer {
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compatible = "ezchip,nps400-timer1";
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clocks = <&sysclk>;
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};
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