mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 14:38:02 +07:00
7aec2fd74a
This reverts commit 8ba671efdb.
As reported by kbuild test robot <fengguang.wu@intel.com>:
In file included from arch/arm/boot/dts/mt2701-evb.dts:16:0:
>> arch/arm/boot/dts/mt2701.dtsi:18:28: fatal error: mt2701-pinfunc.h: No such file or directory
#include "mt2701-pinfunc.h"
^
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
159 lines
3.8 KiB
Plaintext
159 lines
3.8 KiB
Plaintext
/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Erin.Lo <erin.lo@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton64.dtsi"
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/ {
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compatible = "mediatek,mt2701";
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interrupt-parent = <&sysirq>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt81xx-tz-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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trustzone-bootinfo@80002000 {
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compatible = "mediatek,trustzone-bootinfo";
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reg = <0 0x80002000 0 0x1000>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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uart_clk: dummy26m {
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt2701-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt2701-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt2701-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x1000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt2701-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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status = "disabled";
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};
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};
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