mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-22 21:39:35 +07:00
1d17cbfbb5
On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updated accordingly. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
32 lines
1.1 KiB
Plaintext
32 lines
1.1 KiB
Plaintext
Inside Secure SafeXcel cryptographic engine
|
|
|
|
Required properties:
|
|
- compatible: Should be "inside-secure,safexcel-eip197" or
|
|
"inside-secure,safexcel-eip97".
|
|
- reg: Base physical address of the engine and length of memory mapped region.
|
|
- interrupts: Interrupt numbers for the rings and engine.
|
|
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
|
|
|
|
Optional properties:
|
|
- clocks: Reference to the crypto engine clocks, the second clock is
|
|
needed for the Armada 7K/8K SoCs.
|
|
- clock-names: mandatory if there is a second clock, in this case the
|
|
name must be "core" for the first clock and "reg" for
|
|
the second one.
|
|
|
|
Example:
|
|
|
|
crypto: crypto@800000 {
|
|
compatible = "inside-secure,safexcel-eip197";
|
|
reg = <0x800000 0x200000>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
|
|
"eip";
|
|
clocks = <&cpm_syscon0 1 26>;
|
|
};
|