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776f265e27
Add support for flash-based bad block table using Marvell's custom in-flash bad block table layout. The support is enabled a 'flash_bbt' platform data or device tree parameter. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
36 lines
868 B
Plaintext
36 lines
868 B
Plaintext
PXA3xx NAND DT bindings
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Required properties:
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- compatible: Should be set to one of the following:
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marvell,pxa3xx-nand
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marvell,armada370-nand
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- reg: The register base for the controller
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- interrupts: The interrupt to map
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- #address-cells: Set to <1> if the node includes partitions
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Optional properties:
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- marvell,nand-enable-arbiter: Set to enable the bus arbiter
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- marvell,nand-keep-config: Set to keep the NAND controller config as set
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by the bootloader
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- num-cs: Number of chipselect lines to usw
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- nand-on-flash-bbt: boolean to enable on flash bbt option if
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not present false
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Example:
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nand0: nand@43100000 {
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compatible = "marvell,pxa3xx-nand";
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reg = <0x43100000 90>;
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interrupts = <45>;
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#address-cells = <1>;
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marvell,nand-enable-arbiter;
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marvell,nand-keep-config;
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num-cs = <1>;
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/* partitions (optional) */
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};
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