mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 09:26:44 +07:00
0895ecda79
The hugepage arch code provides a number of hook functions/macros which mirror the functionality of various normal page pte access functions. Various changes in the normal page accessors (in particular BenH's recent changes to the handling of lazy icache flushing and PAGE_EXEC) have caused the hugepage versions to get out of sync with the originals. In some cases, this is a bug, at least on some MMU types. One of the reasons that some hooks were not identical to the normal page versions, is that the fact we're dealing with a hugepage needed to be passed down do use the correct dcache-icache flush function. This patch makes the main flush_dcache_icache_page() function hugepage aware (by checking for the PageCompound flag). That in turn means we can make set_huge_pte_at() just a call to set_pte_at() bringing it back into sync. As a bonus, this lets us remove the hash_huge_page_do_lazy_icache() function, replacing it with a call to the hash_page_do_lazy_icache() function it was based on. Some other hugepage pte access hooks - huge_ptep_get_and_clear() and huge_ptep_clear_flush() - are not so easily unified, but this patch at least brings them back into sync with the current versions of the corresponding normal page functions. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
451 lines
14 KiB
C
451 lines
14 KiB
C
#ifndef _ASM_POWERPC_MMU_HASH64_H_
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#define _ASM_POWERPC_MMU_HASH64_H_
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/*
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* PowerPC64 memory management structures
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*
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* Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
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* PPC64 rework.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/asm-compat.h>
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#include <asm/page.h>
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/*
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* Segment table
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*/
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#define STE_ESID_V 0x80
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#define STE_ESID_KS 0x20
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#define STE_ESID_KP 0x10
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#define STE_ESID_N 0x08
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#define STE_VSID_SHIFT 12
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/* Location of cpu0's segment table */
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#define STAB0_PAGE 0x6
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#define STAB0_OFFSET (STAB0_PAGE << 12)
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#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
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#ifndef __ASSEMBLY__
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extern char initial_stab[];
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#endif /* ! __ASSEMBLY */
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/*
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* SLB
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*/
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#define SLB_NUM_BOLTED 3
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#define SLB_CACHE_ENTRIES 8
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#define SLB_MIN_SIZE 32
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/* Bits in the SLB ESID word */
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#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
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/* Bits in the SLB VSID word */
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#define SLB_VSID_SHIFT 12
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#define SLB_VSID_SHIFT_1T 24
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#define SLB_VSID_SSIZE_SHIFT 62
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#define SLB_VSID_B ASM_CONST(0xc000000000000000)
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#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
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#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
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#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
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#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
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#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
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#define SLB_VSID_L ASM_CONST(0x0000000000000100)
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#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
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#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
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#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
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#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
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#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
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#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
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#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
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#define SLB_VSID_KERNEL (SLB_VSID_KP)
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#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
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#define SLBIE_C (0x08000000)
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#define SLBIE_SSIZE_SHIFT 25
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/*
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* Hash table
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*/
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#define HPTES_PER_GROUP 8
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#define HPTE_V_SSIZE_SHIFT 62
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#define HPTE_V_AVPN_SHIFT 7
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#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
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#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
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#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
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#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
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#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
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#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
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#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
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#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
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#define HPTE_R_TS ASM_CONST(0x4000000000000000)
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#define HPTE_R_RPN_SHIFT 12
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#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
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#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
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#define HPTE_R_PP ASM_CONST(0x0000000000000003)
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#define HPTE_R_N ASM_CONST(0x0000000000000004)
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#define HPTE_R_C ASM_CONST(0x0000000000000080)
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#define HPTE_R_R ASM_CONST(0x0000000000000100)
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#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
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#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
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/* Values for PP (assumes Ks=0, Kp=1) */
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/* pp0 will always be 0 for linux */
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#define PP_RWXX 0 /* Supervisor read/write, User none */
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#define PP_RWRX 1 /* Supervisor read/write, User read */
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#define PP_RWRW 2 /* Supervisor read/write, User read/write */
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#define PP_RXRX 3 /* Supervisor read, User read */
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#ifndef __ASSEMBLY__
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struct hash_pte {
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unsigned long v;
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unsigned long r;
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};
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extern struct hash_pte *htab_address;
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extern unsigned long htab_size_bytes;
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extern unsigned long htab_hash_mask;
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/*
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* Page size definition
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*
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* shift : is the "PAGE_SHIFT" value for that page size
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* sllp : is a bit mask with the value of SLB L || LP to be or'ed
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* directly to a slbmte "vsid" value
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* penc : is the HPTE encoding mask for the "LP" field:
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*
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*/
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struct mmu_psize_def
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{
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unsigned int shift; /* number of bits */
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unsigned int penc; /* HPTE encoding */
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unsigned int tlbiel; /* tlbiel supported for that page size */
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unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
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unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
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};
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#endif /* __ASSEMBLY__ */
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/*
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* Segment sizes.
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* These are the values used by hardware in the B field of
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* SLB entries and the first dword of MMU hashtable entries.
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* The B field is 2 bits; the values 2 and 3 are unused and reserved.
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*/
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#define MMU_SEGSIZE_256M 0
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#define MMU_SEGSIZE_1T 1
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#ifndef __ASSEMBLY__
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/*
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* The current system page and segment sizes
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*/
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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extern int mmu_linear_psize;
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extern int mmu_virtual_psize;
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extern int mmu_vmalloc_psize;
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extern int mmu_vmemmap_psize;
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extern int mmu_io_psize;
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extern int mmu_kernel_ssize;
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extern int mmu_highuser_ssize;
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extern u16 mmu_slb_size;
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extern unsigned long tce_alloc_start, tce_alloc_end;
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/*
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* If the processor supports 64k normal pages but not 64k cache
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* inhibited pages, we have to be prepared to switch processes
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* to use 4k pages when they create cache-inhibited mappings.
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* If this is the case, mmu_ci_restrictions will be set to 1.
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*/
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extern int mmu_ci_restrictions;
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/*
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* This function sets the AVPN and L fields of the HPTE appropriately
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* for the page size
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*/
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static inline unsigned long hpte_encode_v(unsigned long va, int psize,
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int ssize)
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{
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unsigned long v;
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v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
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v <<= HPTE_V_AVPN_SHIFT;
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if (psize != MMU_PAGE_4K)
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v |= HPTE_V_LARGE;
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v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
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return v;
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}
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/*
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* This function sets the ARPN, and LP fields of the HPTE appropriately
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* for the page size. We assume the pa is already "clean" that is properly
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* aligned for the requested page size
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*/
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static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
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{
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unsigned long r;
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/* A 4K page needs no special encoding */
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if (psize == MMU_PAGE_4K)
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return pa & HPTE_R_RPN;
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else {
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unsigned int penc = mmu_psize_defs[psize].penc;
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unsigned int shift = mmu_psize_defs[psize].shift;
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return (pa & ~((1ul << shift) - 1)) | (penc << 12);
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}
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return r;
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}
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/*
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* Build a VA given VSID, EA and segment size
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*/
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static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
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int ssize)
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{
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if (ssize == MMU_SEGSIZE_256M)
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return (vsid << 28) | (ea & 0xfffffffUL);
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return (vsid << 40) | (ea & 0xffffffffffUL);
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}
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/*
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* This hashes a virtual address
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*/
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static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
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int ssize)
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{
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unsigned long hash, vsid;
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if (ssize == MMU_SEGSIZE_256M) {
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hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
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} else {
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vsid = va >> 40;
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hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
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}
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return hash & 0x7fffffffffUL;
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}
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extern int __hash_page_4K(unsigned long ea, unsigned long access,
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unsigned long vsid, pte_t *ptep, unsigned long trap,
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unsigned int local, int ssize, int subpage_prot);
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extern int __hash_page_64K(unsigned long ea, unsigned long access,
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unsigned long vsid, pte_t *ptep, unsigned long trap,
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unsigned int local, int ssize);
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struct mm_struct;
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unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
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extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
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int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
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pte_t *ptep, unsigned long trap, int local, int ssize,
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unsigned int shift, unsigned int mmu_psize);
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extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
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unsigned long pstart, unsigned long prot,
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int psize, int ssize);
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extern void add_gpage(unsigned long addr, unsigned long page_size,
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unsigned long number_of_pages);
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extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
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extern void hpte_init_native(void);
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extern void hpte_init_lpar(void);
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extern void hpte_init_iSeries(void);
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extern void hpte_init_beat(void);
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extern void hpte_init_beat_v3(void);
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extern void stabs_alloc(void);
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extern void slb_initialize(void);
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extern void slb_flush_and_rebolt(void);
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extern void stab_initialize(unsigned long stab);
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extern void slb_vmalloc_update(void);
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extern void slb_set_size(u16 size);
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#endif /* __ASSEMBLY__ */
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/*
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* VSID allocation
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*
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* We first generate a 36-bit "proto-VSID". For kernel addresses this
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* is equal to the ESID, for user addresses it is:
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* (context << 15) | (esid & 0x7fff)
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*
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* The two forms are distinguishable because the top bit is 0 for user
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* addresses, whereas the top two bits are 1 for kernel addresses.
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* Proto-VSIDs with the top two bits equal to 0b10 are reserved for
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* now.
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*
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* The proto-VSIDs are then scrambled into real VSIDs with the
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* multiplicative hash:
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*
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* VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
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* where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
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* VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
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*
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* This scramble is only well defined for proto-VSIDs below
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* 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
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* reserved. VSID_MULTIPLIER is prime, so in particular it is
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* co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
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* Because the modulus is 2^n-1 we can compute it efficiently without
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* a divide or extra multiply (see below).
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*
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* This scheme has several advantages over older methods:
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*
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* - We have VSIDs allocated for every kernel address
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* (i.e. everything above 0xC000000000000000), except the very top
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* segment, which simplifies several things.
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*
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* - We allow for 15 significant bits of ESID and 20 bits of
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* context for user addresses. i.e. 8T (43 bits) of address space for
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* up to 1M contexts (although the page table structure and context
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* allocation will need changes to take advantage of this).
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*
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* - The scramble function gives robust scattering in the hash
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* table (at least based on some initial results). The previous
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* method was more susceptible to pathological cases giving excessive
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* hash collisions.
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*/
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/*
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* WARNING - If you change these you must make sure the asm
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* implementations in slb_allocate (slb_low.S), do_stab_bolted
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* (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
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*
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* You'll also need to change the precomputed VSID values in head.S
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* which are used by the iSeries firmware.
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*/
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#define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
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#define VSID_BITS_256M 36
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#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
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#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
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#define VSID_BITS_1T 24
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#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
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#define CONTEXT_BITS 19
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#define USER_ESID_BITS 16
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#define USER_ESID_BITS_1T 4
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#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
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/*
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* This macro generates asm code to compute the VSID scramble
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* function. Used in slb_allocate() and do_stab_bolted. The function
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* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
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*
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* rt = register continaing the proto-VSID and into which the
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* VSID will be stored
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* rx = scratch register (clobbered)
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*
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* - rt and rx must be different registers
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* - The answer will end up in the low VSID_BITS bits of rt. The higher
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* bits may contain other garbage, so you may need to mask the
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* result.
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*/
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#define ASM_VSID_SCRAMBLE(rt, rx, size) \
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lis rx,VSID_MULTIPLIER_##size@h; \
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ori rx,rx,VSID_MULTIPLIER_##size@l; \
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mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
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\
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srdi rx,rt,VSID_BITS_##size; \
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clrldi rt,rt,(64-VSID_BITS_##size); \
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add rt,rt,rx; /* add high and low bits */ \
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/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
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* 2^36-1+2^28-1. That in particular means that if r3 >= \
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* 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
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* the bit clear, r3 already has the answer we want, if it \
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* doesn't, the answer is the low 36 bits of r3+1. So in all \
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* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
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addi rx,rt,1; \
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srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
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add rt,rt,rx
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#ifndef __ASSEMBLY__
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typedef unsigned long mm_context_id_t;
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typedef struct {
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mm_context_id_t id;
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u16 user_psize; /* page size index */
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#ifdef CONFIG_PPC_MM_SLICES
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u64 low_slices_psize; /* SLB page size encodings */
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u64 high_slices_psize; /* 4 bits per slice for now */
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#else
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u16 sllp; /* SLB page size encoding */
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#endif
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unsigned long vdso_base;
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} mm_context_t;
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#if 0
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/*
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* The code below is equivalent to this function for arguments
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* < 2^VSID_BITS, which is all this should ever be called
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* with. However gcc is not clever enough to compute the
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* modulus (2^n-1) without a second multiply.
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*/
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#define vsid_scrample(protovsid, size) \
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((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
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#else /* 1 */
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#define vsid_scramble(protovsid, size) \
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({ \
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unsigned long x; \
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x = (protovsid) * VSID_MULTIPLIER_##size; \
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x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
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(x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
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})
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#endif /* 1 */
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/* This is only valid for addresses >= PAGE_OFFSET */
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static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
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{
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if (ssize == MMU_SEGSIZE_256M)
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return vsid_scramble(ea >> SID_SHIFT, 256M);
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return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
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}
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/* Returns the segment size indicator for a user address */
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static inline int user_segment_size(unsigned long addr)
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{
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/* Use 1T segments if possible for addresses >= 1T */
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if (addr >= (1UL << SID_SHIFT_1T))
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return mmu_highuser_ssize;
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return MMU_SEGSIZE_256M;
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}
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/* This is only valid for user addresses (which are below 2^44) */
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|
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
|
|
int ssize)
|
|
{
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|
if (ssize == MMU_SEGSIZE_256M)
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|
return vsid_scramble((context << USER_ESID_BITS)
|
|
| (ea >> SID_SHIFT), 256M);
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|
return vsid_scramble((context << USER_ESID_BITS_1T)
|
|
| (ea >> SID_SHIFT_1T), 1T);
|
|
}
|
|
|
|
/*
|
|
* This is only used on legacy iSeries in lparmap.c,
|
|
* hence the 256MB segment assumption.
|
|
*/
|
|
#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER_256M) % \
|
|
VSID_MODULUS_256M)
|
|
#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
|