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ec431eae8f
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.
One possible solution to this problem is to reprogram the NOA muxes
when we switch to a new context. We initially tried this in the
workaround batchbuffer but some concerns where raised about the cost
of reprogramming at every context switch. This solution is also not
without consequences from the userspace point of view. Reprogramming
of the muxes can only happen once the powergating configuration has
changed (which happens after context switch). This means for a window
of time during the recording, counters recorded by the OA unit might
be invalid. This requires userspace dealing with OA reports to discard
the invalid values.
Minimizing the reprogramming could be implemented by tracking of the
last programmed configuration somewhere in GGTT and use MI_PREDICATE
to discard some of the programming commands, but the command streamer
would still have to parse all the MI_LRI instructions in the
workaround batchbuffer.
Another solution, which this change implements, is to simply disregard
the user requested configuration for the period of time when i915/perf
is active.
On most platforms there are no issues with this apart from a performance
penality for some media workloads that benefit from running on a partially
powergated GPU. We already prevent RC6 from affecting the programming so
it doesn't sound completely unreasonable to hold on powergating for the
same reason.
On Icelake however there would a functional problem if the slices not-
containing the VME block were left enabled with a running media workload
which explicitly disabled them. To avoid a GPU hang in this case, on
Icelake we lock the enablement to only slices which contain VME blocks.
Downside is that it means degraded GPU performance when OA is active but
there is no known alternative solution for this.
v2: Leave RPCS programming in intel_lrc.c (Lionel)
v3: Update for s/union intel_sseu/struct intel_sseu/ (Lionel)
More to_intel_context() (Tvrtko)
s/dev_priv/i915/ (Tvrtko)
Tvrtko Ursulin:
v4:
* Rebase for make_rpcs changes.
v5:
* Apply OA restriction from make_rpcs directly.
v6:
* Rebase for context image setup changes.
v7:
* Move stream assignment before metric enable.
v8-9:
* Rebase.
v10:
* Squashed with ICL support patch.
Bspec: 21140
Co-developed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v9
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190205095032.22673-2-tvrtko.ursulin@linux.intel.com
118 lines
4.6 KiB
C
118 lines
4.6 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#include "intel_ringbuffer.h"
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#include "i915_gem_context.h"
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/* Execlists regs */
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#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
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#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
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#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
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#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
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#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
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#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
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#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
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#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
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#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
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#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
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#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
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#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
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#define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510)
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#define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550)
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#define EL_CTRL_LOAD (1 << 0)
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/* The docs specify that the write pointer wraps around after 5h, "After status
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* is written out to the last available status QW at offset 5h, this pointer
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* wraps to 0."
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*
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* Therefore, one must infer than even though there are 3 bits available, 6 and
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* 7 appear to be * reserved.
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*/
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x7
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#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
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#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
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#define GEN8_CSB_WRITE_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
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#define GEN8_CSB_READ_PTR(csb_status) \
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(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
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enum {
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INTEL_CONTEXT_SCHEDULE_IN = 0,
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INTEL_CONTEXT_SCHEDULE_OUT,
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INTEL_CONTEXT_SCHEDULE_PREEMPTED,
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};
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/* Logical Rings */
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void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
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int logical_render_ring_init(struct intel_engine_cs *engine);
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int logical_xcs_ring_init(struct intel_engine_cs *engine);
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/* Logical Ring Contexts */
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/*
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* We allocate a header at the start of the context image for our own
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* use, therefore the actual location of the logical state is offset
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* from the start of the VMA. The layout is
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*
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* | [guc] | [hwsp] [logical state] |
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* |<- our header ->|<- context image ->|
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*
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*/
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/* The first page is used for sharing data with the GuC */
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#define LRC_GUCSHR_PN (0)
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#define LRC_GUCSHR_SZ (1)
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/* At the start of the context image is its per-process HWS page */
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#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + LRC_GUCSHR_SZ)
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#define LRC_PPHWSP_SZ (1)
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/* Finally we have the logical state for the context */
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#define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
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/*
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* Currently we include the PPHWSP in __intel_engine_context_size() so
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* the size of the header is synonymous with the start of the PPHWSP.
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*/
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#define LRC_HEADER_PAGES LRC_PPHWSP_PN
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struct drm_printer;
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struct drm_i915_private;
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struct i915_gem_context;
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void intel_lr_context_resume(struct drm_i915_private *dev_priv);
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void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
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void intel_execlists_show_requests(struct intel_engine_cs *engine,
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struct drm_printer *m,
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void (*show_request)(struct drm_printer *m,
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struct i915_request *rq,
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const char *prefix),
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unsigned int max);
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u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu);
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#endif /* _INTEL_LRC_H_ */
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