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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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192f0f8e9d
Notable changes: - Removal of the NPU DMA code, used by the out-of-tree Nvidia driver, as well as some other functions only used by drivers that haven't (yet?) made it upstream. - A fix for a bug in our handling of hardware watchpoints (eg. perf record -e mem: ...) which could lead to register corruption and kernel crashes. - Enable HAVE_ARCH_HUGE_VMAP, which allows us to use large pages for vmalloc when using the Radix MMU. - A large but incremental rewrite of our exception handling code to use gas macros rather than multiple levels of nested CPP macros. And the usual small fixes, cleanups and improvements. Thanks to: Alastair D'Silva, Alexey Kardashevskiy, Andreas Schwab, Aneesh Kumar K.V, Anju T Sudhakar, Anton Blanchard, Arnd Bergmann, Athira Rajeev, Cédric Le Goater, Christian Lamparter, Christophe Leroy, Christophe Lombard, Christoph Hellwig, Daniel Axtens, Denis Efremov, Enrico Weigelt, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven, Geliang Tang, Gen Zhang, Greg Kroah-Hartman, Greg Kurz, Gustavo Romero, Krzysztof Kozlowski, Madhavan Srinivasan, Masahiro Yamada, Mathieu Malaterre, Michael Neuling, Nathan Lynch, Naveen N. Rao, Nicholas Piggin, Nishad Kamdar, Oliver O'Halloran, Qian Cai, Ravi Bangoria, Sachin Sant, Sam Bobroff, Satheesh Rajendran, Segher Boessenkool, Shaokun Zhang, Shawn Anastasio, Stewart Smith, Suraj Jitindar Singh, Thiago Jung Bauermann, YueHaibing. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdKVoLAAoJEFHr6jzI4aWA0kIP/A6shIbbE7H5W2hFrqt/PPPK 3+VrvPKbOFF+W6hcE/RgSZmEnUo0svdNjHUd/eMfFS1vb/uRt2QDdrsHUNNwURQL M2mcLXFwYpnjSjb/XMgDbHpAQxjeGfTdYLonUIejN7Rk8KQUeLyKQ3SBn6kfMc46 DnUUcPcjuRGaETUmVuZZ4e40ZWbJp8PKDrSJOuUrTPXMaK5ciNbZk5mCWXGbYl6G BMQAyv4ld/417rNTjBEP/T2foMJtioAt4W6mtlgdkOTdIEZnFU67nNxDBthNSu2c 95+I+/sML4KOp1R4yhqLSLIDDbc3bg3c99hLGij0d948z3bkSZ8bwnPaUuy70C4v U8rvl/+N6C6H3DgSsPE/Gnkd8DnudqWY8nULc+8p3fXljGwww6/Qgt+6yCUn8BdW WgixkSjKgjDmzTw8trIUNEqORrTVle7cM2hIyIK2Q5T4kWzNQxrLZ/x/3wgoYjUa 1KwIzaRo5JKZ9D3pJnJ5U+knE2/90rJIyfcp0W6ygyJsWKi2GNmq1eN3sKOw0IxH Tg86RENIA/rEMErNOfP45sLteMuTR7of7peCG3yumIOZqsDVYAzerpvtSgip2cvK aG+9HcYlBFOOOF9Dabi8GXsTBLXLfwiyjjLSpA9eXPwW8KObgiNfTZa7ujjTPvis 4mk9oukFTFUpfhsMmI3T =3dBZ -----END PGP SIGNATURE----- Merge tag 'powerpc-5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc updates from Michael Ellerman: "Notable changes: - Removal of the NPU DMA code, used by the out-of-tree Nvidia driver, as well as some other functions only used by drivers that haven't (yet?) made it upstream. - A fix for a bug in our handling of hardware watchpoints (eg. perf record -e mem: ...) which could lead to register corruption and kernel crashes. - Enable HAVE_ARCH_HUGE_VMAP, which allows us to use large pages for vmalloc when using the Radix MMU. - A large but incremental rewrite of our exception handling code to use gas macros rather than multiple levels of nested CPP macros. And the usual small fixes, cleanups and improvements. Thanks to: Alastair D'Silva, Alexey Kardashevskiy, Andreas Schwab, Aneesh Kumar K.V, Anju T Sudhakar, Anton Blanchard, Arnd Bergmann, Athira Rajeev, Cédric Le Goater, Christian Lamparter, Christophe Leroy, Christophe Lombard, Christoph Hellwig, Daniel Axtens, Denis Efremov, Enrico Weigelt, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven, Geliang Tang, Gen Zhang, Greg Kroah-Hartman, Greg Kurz, Gustavo Romero, Krzysztof Kozlowski, Madhavan Srinivasan, Masahiro Yamada, Mathieu Malaterre, Michael Neuling, Nathan Lynch, Naveen N. Rao, Nicholas Piggin, Nishad Kamdar, Oliver O'Halloran, Qian Cai, Ravi Bangoria, Sachin Sant, Sam Bobroff, Satheesh Rajendran, Segher Boessenkool, Shaokun Zhang, Shawn Anastasio, Stewart Smith, Suraj Jitindar Singh, Thiago Jung Bauermann, YueHaibing" * tag 'powerpc-5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (163 commits) powerpc/powernv/idle: Fix restore of SPRN_LDBAR for POWER9 stop state. powerpc/eeh: Handle hugepages in ioremap space ocxl: Update for AFU descriptor template version 1.1 powerpc/boot: pass CONFIG options in a simpler and more robust way powerpc/boot: add {get, put}_unaligned_be32 to xz_config.h powerpc/irq: Don't WARN continuously in arch_local_irq_restore() powerpc/module64: Use symbolic instructions names. powerpc/module32: Use symbolic instructions names. powerpc: Move PPC_HA() PPC_HI() and PPC_LO() to ppc-opcode.h powerpc/module64: Fix comment in R_PPC64_ENTRY handling powerpc/boot: Add lzo support for uImage powerpc/boot: Add lzma support for uImage powerpc/boot: don't force gzipped uImage powerpc/8xx: Add microcode patch to move SMC parameter RAM. powerpc/8xx: Use IO accessors in microcode programming. powerpc/8xx: replace #ifdefs by IS_ENABLED() in microcode.c powerpc/8xx: refactor programming of microcode CPM params. powerpc/8xx: refactor printing of microcode patch name. powerpc/8xx: Refactor microcode write powerpc/8xx: refactor writing of CPM microcode arrays ...
167 lines
4.1 KiB
C
167 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2016-17 IBM Corp.
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*/
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#ifndef _ASM_POWERPC_VAS_H
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#define _ASM_POWERPC_VAS_H
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struct vas_window;
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/*
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* Min and max FIFO sizes are based on Version 1.05 Section 3.1.4.25
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* (Local FIFO Size Register) of the VAS workbook.
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*/
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#define VAS_RX_FIFO_SIZE_MIN (1 << 10) /* 1KB */
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#define VAS_RX_FIFO_SIZE_MAX (8 << 20) /* 8MB */
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/*
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* Threshold Control Mode: Have paste operation fail if the number of
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* requests in receive FIFO exceeds a threshold.
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*
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* NOTE: No special error code yet if paste is rejected because of these
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* limits. So users can't distinguish between this and other errors.
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*/
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#define VAS_THRESH_DISABLED 0
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#define VAS_THRESH_FIFO_GT_HALF_FULL 1
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#define VAS_THRESH_FIFO_GT_QTR_FULL 2
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#define VAS_THRESH_FIFO_GT_EIGHTH_FULL 3
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/*
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* Get/Set bit fields
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*/
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#define GET_FIELD(m, v) (((v) & (m)) >> MASK_LSH(m))
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#define MASK_LSH(m) (__builtin_ffsl(m) - 1)
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#define SET_FIELD(m, v, val) \
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(((v) & ~(m)) | ((((typeof(v))(val)) << MASK_LSH(m)) & (m)))
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/*
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* Co-processor Engine type.
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*/
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enum vas_cop_type {
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VAS_COP_TYPE_FAULT,
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VAS_COP_TYPE_842,
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VAS_COP_TYPE_842_HIPRI,
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VAS_COP_TYPE_GZIP,
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VAS_COP_TYPE_GZIP_HIPRI,
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VAS_COP_TYPE_FTW,
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VAS_COP_TYPE_MAX,
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};
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/*
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* Receive window attributes specified by the (in-kernel) owner of window.
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*/
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struct vas_rx_win_attr {
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void *rx_fifo;
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int rx_fifo_size;
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int wcreds_max;
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bool pin_win;
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bool rej_no_credit;
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bool tx_wcred_mode;
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bool rx_wcred_mode;
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bool tx_win_ord_mode;
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bool rx_win_ord_mode;
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bool data_stamp;
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bool nx_win;
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bool fault_win;
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bool user_win;
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bool notify_disable;
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bool intr_disable;
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bool notify_early;
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int lnotify_lpid;
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int lnotify_pid;
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int lnotify_tid;
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u32 pswid;
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int tc_mode;
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};
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/*
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* Window attributes specified by the in-kernel owner of a send window.
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*/
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struct vas_tx_win_attr {
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enum vas_cop_type cop;
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int wcreds_max;
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int lpid;
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int pidr; /* hardware PID (from SPRN_PID) */
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int pid; /* linux process id */
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int pswid;
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int rsvd_txbuf_count;
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int tc_mode;
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bool user_win;
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bool pin_win;
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bool rej_no_credit;
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bool rsvd_txbuf_enable;
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bool tx_wcred_mode;
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bool rx_wcred_mode;
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bool tx_win_ord_mode;
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bool rx_win_ord_mode;
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};
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/*
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* Helper to map a chip id to VAS id.
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* For POWER9, this is a 1:1 mapping. In the future this maybe a 1:N
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* mapping in which case, we will need to update this helper.
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*
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* Return the VAS id or -1 if no matching vasid is found.
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*/
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int chip_to_vas_id(int chipid);
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/*
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* Helper to initialize receive window attributes to defaults for an
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* NX window.
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*/
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void vas_init_rx_win_attr(struct vas_rx_win_attr *rxattr, enum vas_cop_type cop);
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/*
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* Open a VAS receive window for the instance of VAS identified by @vasid
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* Use @attr to initialize the attributes of the window.
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*
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* Return a handle to the window or ERR_PTR() on error.
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*/
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struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop,
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struct vas_rx_win_attr *attr);
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/*
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* Helper to initialize send window attributes to defaults for an NX window.
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*/
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extern void vas_init_tx_win_attr(struct vas_tx_win_attr *txattr,
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enum vas_cop_type cop);
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/*
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* Open a VAS send window for the instance of VAS identified by @vasid
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* and the co-processor type @cop. Use @attr to initialize attributes
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* of the window.
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*
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* Note: The instance of VAS must already have an open receive window for
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* the coprocessor type @cop.
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*
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* Return a handle to the send window or ERR_PTR() on error.
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*/
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struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop,
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struct vas_tx_win_attr *attr);
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/*
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* Close the send or receive window identified by @win. For receive windows
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* return -EAGAIN if there are active send windows attached to this receive
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* window.
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*/
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int vas_win_close(struct vas_window *win);
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/*
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* Copy the co-processor request block (CRB) @crb into the local L2 cache.
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*/
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int vas_copy_crb(void *crb, int offset);
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/*
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* Paste a previously copied CRB (see vas_copy_crb()) from the L2 cache to
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* the hardware address associated with the window @win. @re is expected/
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* assumed to be true for NX windows.
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*/
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int vas_paste_crb(struct vas_window *win, int offset, bool re);
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#endif /* __ASM_POWERPC_VAS_H */
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