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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3aa741f395
Currently platform specific private data initialization is done by dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt. As we already have separate platform specific device tree parser dw_mci_socfpga_parse_dt, move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt. We can use the dw_mci_socfpga_priv_init to do some actual platform specific initialization. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
139 lines
3.8 KiB
C
139 lines
3.8 KiB
C
/*
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* Altera SoCFPGA Specific Extensions for Synopsys DW Multimedia Card Interface
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* driver
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*
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* Copyright (C) 2012, Samsung Electronics Co., Ltd.
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* Copyright (C) 2013 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Taken from dw_mmc-exynos.c
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*/
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
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#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7
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#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
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((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
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/* SOCFPGA implementation specific driver private data */
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struct dw_mci_socfpga_priv_data {
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u8 ciu_div; /* card interface unit divisor */
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u32 hs_timing; /* bitmask for CIU clock phase shift */
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struct regmap *sysreg; /* regmap for system manager register */
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};
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static int dw_mci_socfpga_priv_init(struct dw_mci *host)
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{
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return 0;
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}
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static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
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{
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struct dw_mci_socfpga_priv_data *priv = host->priv;
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clk_disable_unprepare(host->ciu_clk);
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regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET,
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priv->hs_timing);
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clk_prepare_enable(host->ciu_clk);
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host->bus_hz /= (priv->ciu_div + 1);
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return 0;
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}
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static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
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{
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struct dw_mci_socfpga_priv_data *priv = host->priv;
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if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK)
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*cmdr |= SDMMC_CMD_USE_HOLD_REG;
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}
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static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
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{
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struct dw_mci_socfpga_priv_data *priv;
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struct device_node *np = host->dev->of_node;
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u32 timing[2];
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u32 div = 0;
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int ret;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(host->dev, "mem alloc failed for private data\n");
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return -ENOMEM;
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}
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priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
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if (IS_ERR(priv->sysreg)) {
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dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
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return PTR_ERR(priv->sysreg);
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}
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ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
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if (ret)
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dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
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priv->ciu_div = div;
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ret = of_property_read_u32_array(np,
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"altr,dw-mshc-sdr-timing", timing, 2);
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if (ret)
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return ret;
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priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
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host->priv = priv;
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return 0;
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}
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static const struct dw_mci_drv_data socfpga_drv_data = {
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.init = dw_mci_socfpga_priv_init,
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.setup_clock = dw_mci_socfpga_setup_clock,
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.prepare_command = dw_mci_socfpga_prepare_command,
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.parse_dt = dw_mci_socfpga_parse_dt,
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};
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static const struct of_device_id dw_mci_socfpga_match[] = {
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{ .compatible = "altr,socfpga-dw-mshc",
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.data = &socfpga_drv_data, },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_socfpga_match);
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int dw_mci_socfpga_probe(struct platform_device *pdev)
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{
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const struct dw_mci_drv_data *drv_data;
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const struct of_device_id *match;
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match = of_match_node(dw_mci_socfpga_match, pdev->dev.of_node);
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drv_data = match->data;
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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static struct platform_driver dw_mci_socfpga_pltfm_driver = {
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.probe = dw_mci_socfpga_probe,
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.remove = __exit_p(dw_mci_pltfm_remove),
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.driver = {
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.name = "dwmmc_socfpga",
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.of_match_table = of_match_ptr(dw_mci_socfpga_match),
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.pm = &dw_mci_pltfm_pmops,
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},
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};
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module_platform_driver(dw_mci_socfpga_pltfm_driver);
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MODULE_DESCRIPTION("Altera SOCFPGA Specific DW-MSHC Driver Extension");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:dwmmc-socfpga");
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