mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 00:40:55 +07:00
d861196163
v2: fixes from Russell King:
- include linux/io.h instead of asm/io.h
- fix whitespace in Kconfig
- Use spin_lock_init to initialize lock
- Return -ENOSYS instead of BUG for unimplemented clock ops
- Use proper return values in tegra2 clock ops
additional changes:
- Rename some clocks to match dev_ids
- add rate propagation
- add debugfs entries
- add support for clock listed in clk_lookup under multiple dev_ids
v3:
- Replace per-clock locking with global clock lock
- Autodetect clock state on init
- Let clock dividers pick next lower possible frequency
- Add support for clock init tables
- Minor bug fixes
- Fix checkpatch issues
Signed-off-by: Colin Cross <ccross@android.com>
148 lines
3.3 KiB
C
148 lines
3.3 KiB
C
/*
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* arch/arm/mach-tegra/include/mach/clock.h
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_CLOCK_H
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#define __MACH_TEGRA_CLOCK_H
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#include <linux/list.h>
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#include <asm/clkdev.h>
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#define DIV_BUS (1 << 0)
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#define DIV_U71 (1 << 1)
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#define DIV_U71_FIXED (1 << 2)
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#define DIV_2 (1 << 3)
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#define PLL_FIXED (1 << 4)
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#define PLL_HAS_CPCON (1 << 5)
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#define MUX (1 << 6)
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#define PLLD (1 << 7)
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#define PERIPH_NO_RESET (1 << 8)
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#define PERIPH_NO_ENB (1 << 9)
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#define PERIPH_EMC_ENB (1 << 10)
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#define PERIPH_MANUAL_RESET (1 << 11)
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#define PLL_ALT_MISC_REG (1 << 12)
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#define ENABLE_ON_INIT (1 << 28)
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struct clk;
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struct clk_mux_sel {
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struct clk *input;
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u32 value;
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};
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struct clk_pll_table {
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unsigned long input_rate;
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unsigned long output_rate;
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u16 n;
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u16 m;
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u8 p;
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u8 cpcon;
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};
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struct clk_ops {
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void (*init)(struct clk *);
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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void (*recalc)(struct clk *);
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int (*set_parent)(struct clk *, struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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unsigned long (*get_rate)(struct clk *);
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long (*round_rate)(struct clk *, unsigned long);
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unsigned long (*recalculate_rate)(struct clk *);
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};
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enum clk_state {
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UNINITIALIZED = 0,
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ON,
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OFF,
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};
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struct clk {
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/* node for master clocks list */
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struct list_head node;
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struct list_head children; /* list of children */
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struct list_head sibling; /* node for children */
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dent;
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struct dentry *parent_dent;
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#endif
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struct clk_ops *ops;
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struct clk *parent;
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struct clk_lookup lookup;
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unsigned long rate;
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u32 flags;
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u32 refcnt;
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const char *name;
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u32 reg;
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u32 reg_shift;
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unsigned int clk_num;
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enum clk_state state;
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#ifdef CONFIG_DEBUG_FS
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bool set;
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#endif
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/* PLL */
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unsigned long input_min;
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unsigned long input_max;
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unsigned long cf_min;
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unsigned long cf_max;
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unsigned long vco_min;
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unsigned long vco_max;
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u32 m;
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u32 n;
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u32 p;
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u32 cpcon;
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const struct clk_pll_table *pll_table;
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/* DIV */
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u32 div;
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u32 mul;
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/* MUX */
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const struct clk_mux_sel *inputs;
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u32 sel;
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u32 reg_mask;
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};
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struct clk_duplicate {
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const char *name;
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struct clk_lookup lookup;
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};
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struct tegra_clk_init_table {
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const char *name;
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const char *parent;
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unsigned long rate;
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bool enabled;
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};
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void tegra2_init_clocks(void);
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void tegra2_periph_reset_deassert(struct clk *c);
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void tegra2_periph_reset_assert(struct clk *c);
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void clk_init(struct clk *clk);
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struct clk *tegra_get_clock_by_name(const char *name);
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unsigned long clk_measure_input_freq(void);
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void clk_disable_locked(struct clk *c);
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int clk_enable_locked(struct clk *c);
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int clk_set_parent_locked(struct clk *c, struct clk *parent);
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int clk_reparent(struct clk *c, struct clk *parent);
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void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
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#endif
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